A wideband digital receiver with a 50% coverage rate is proposed and implemented based on multiple filter bank theory and the FFT method. This system divides the entire sampling frequency band into several parallel channels, enabling full probability interception of signals. It serves as an ideal front-end for detecting frequency-hopping, burst, and adaptive communication signals. Primarily used in software-defined radio and electronic warfare applications, this receiver focuses on the channelization principle, software simulation, and hardware implementation. Algorithms, programs, and hardware platforms are designed to meet practical engineering requirements, achieving digital channelization across 8 channels within the 0–100 MHz frequency range.
In today’s complex and dense electronic warfare environment, the spectrum is continuously expanding, placing higher demands on the accurate reception of signals by wideband digital receivers. Traditional digital receivers may suffer from dead zones between adjacent channels, leading to potential signal loss. The improved polyphase filter eliminates these issues by avoiding equal channel numbers and extraction multiples, offering more flexibility. With their high-speed processing capabilities, large number of multipliers, memories, and logic units, FPGAs have become a key tool in designing high-speed digital filters, providing significant advantages in such applications.
**1. Principle of Digital Channelization**
The input signal x[n] is the A/D converted data. In this digital receiver, each bandpass filter is derived from a prototype low-pass filter hâ‚€[n]. If hâ‚€[n] is a real-valued causal low-pass filter of length N, then hâ‚€[n] = {h[0], h[1], ..., h[N-1]}. This low-pass filter can be transformed into a set of bandpass filters. The center frequency of the k-th channel is:
$$ f_k = \frac{f_s}{K} \cdot k $$
For a typical digital receiver, the length N of the prototype low-pass filter is greater than the number of channels K. If N = KP, then:
$$ h_{k,m}(n) = h_0(n - mK + k) $$
After the digital channelization process, the frequency is reduced to 1/M of the original, allowing for M-time extraction. The structure of the multi-filter is generally defined as K = FM, where K is the total number of channels, and M is the decimation factor. The prototype low-pass filter hâ‚€[n] can be decomposed into K-phase components.
The hardware implementation block diagram for F=2 is shown in Figure 2.
**2. Matlab Simulation of the System**
Matlab is widely used in engineering, signal processing, and mathematics for filter design. Using the firpmord function, we can determine the order of the prototype low-pass filter, and the firpm function helps in calculating its coefficients. Assuming a sampling rate of 200 MHz divided into 16 uniform channels, the passband cutoff frequency is 6.25 MHz, and the stopband cutoff frequency is 12.5 MHz. The filter specifications include a passband gain of 1, a stopband gain of 0, a passband ripple of 0.01 dB, and a stopband attenuation of 60 dB.
Based on these parameters, a 96-order FIR filter is obtained. Its frequency response is shown in Figure 3. Since FPGA implementation requires quantized filters, the 10-bit quantized characteristics of the FIR filter are also presented. A 16-times decimation is performed on the prototype filter, and after two interpolations, the multi-phase components are extracted. The digital channelization process is simulated in the Matlab environment, and the results are shown in Figure 5.
As seen in Figure 5, a 25.1 MHz signal is located in the second channel, and the simulation results show that the output amplitude of the second channel is significantly larger than that of other channels, exceeding 60 dB.
**3. Hardware Platform of the Channelized Receiver**
**3.1 Hardware System**
A vector signal source (JUNG JIN SG-1710) generates a signal in the 0–200 MHz range, which passes through a transformer and enters the A/D converter. The system outputs LVDS data and a synchronization clock to the FPGA. A voltage-controlled oscillator generates a 200 MHz differential clock for the A/D. The A/D converter selected is the LTC2242-10, a 10-bit, 250 MSPS, high-IF sampling ADC from Linear, offering a 1.2 GHz analog input bandwidth and requiring 2.5V of power. The FPGA used is the EP2S60F484 from Altera’s Stratix II series, grade C5. The voltage-controlled oscillator is the AD9516-3, which provides multi-output clock distribution with sub-picosecond jitter performance, including an integrated PLL and VCO. It offers four LVDS outputs at 800 MHz, with one output driving the 200 MHz clock for the A/D. The system hardware block diagram is shown in Figure 6.
**3.2 Hardware System Implementation**
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