The Radio Frequency Identification (RFID) system typically consists of a reader and an electronic tag, with the antenna serving as a critical link between them. To maximize the absorption of RF energy from the reader by the passive tag's antenna, it is essential to achieve conjugate impedance matching between the tag antenna and the tag chip. This means that the impedance value of the UHF band passive RFID single chip directly influences the design of the electronic tag antenna, thereby affecting its overall performance.
In the case of UHF band passive RFID tags, the operation relies on reflection modulation, which introduces complex characteristics such as frequency dependency, time variation, and nonlinearity, especially for chips with dimensions smaller than 1 mm². These factors pose significant challenges in accurately measuring the chip’s impedance using conventional methods. Therefore, this paper explores an innovative method for testing the impedance of UHF passive RFID chips under low power consumption conditions.
One of the key challenges in traditional testing is the parasitic capacitance or inductance introduced by leads connecting the chip pads, which can distort the measured impedance. Additionally, the difficulty in controlling lead length and width often results in poor test repeatability. To overcome these issues, this study employs a transmission line impedance matching network, allowing for more accurate and reliable impedance measurements.
According to distributed parameter circuit theory, the characteristic impedance of a transmission line depends on its width and length. In this study, parallel two-wire transmission lines are used due to their wide operational bandwidth and compatibility with frequencies below 1 GHz. The characteristic impedance of such lines is calculated using the formula:
$$ Z_0 = \frac{120}{\sqrt{\varepsilon_r}} \cdot \ln\left(\frac{a}{b}\right) $$
where $ a $ is the distance between the centers of the two conductors, and $ b $ is the width of each conductor.
By leveraging the properties of transmission lines, a matching network is constructed, as shown in Figure 1. This network includes a λ/4 open-circuited transmission line, which acts like a short circuit, and a short-circuited stub connected in parallel. By adjusting the distance between the stub and the chip, the inductive reactance can be modified to achieve conjugate matching with the chip’s impedance.
When the chip and the matching network are conjugately matched, the return loss (S11) at both ends of the chip is minimized, indicating maximum energy absorption. By observing the S11 value, the optimal transmission line impedance $ Z_0 $ and the stub length $ L_\lambda $ can be determined, allowing for the calculation of the chip’s input impedance during normal operation.
Figure 2 illustrates the equivalent circuit of the impedance matching network, where $ Y_{R0} $, $ Y_s $, and $ Y_{chip} $ represent the admittances of the resistor, the stub, and the chip, respectively. Using transmission line theory, the admittance values are calculated to ensure proper matching.
The actual test model, shown in Figure 3, involves connecting the reader to an adjustable attenuator via a coaxial cable, with a reference impedance of 50 Ω. The reader is set to 915 MHz, and the attenuator is adjusted to reduce the input energy to the minimum required for the chip to operate. At this point, the values of $ Z_0 $ and $ L_\lambda $ are recorded and used to calculate the chip’s impedance.
Using ADS simulation software, the impedance test model was validated. When the chip impedance was set to 18.1 - j149 Ω, the optimal transmission line impedance $ Z_0 $ was found to be 250 Ω. The simulation results showed a good match between the standard chip and the impedance network, confirming the effectiveness of the proposed method.
For the actual test, a custom PCB was fabricated based on the simulation results. The center distance of the parallel double line was set to 4.15 mm, and the corresponding $ Z_0 $ values were calculated. A balun was incorporated into the design to improve signal balance and reduce interference. The test results showed that the measured impedance of the NXP_XM chip was 17.1 - j145 Ω, while the Impinj_Monza4 chip had an impedance of 10.2 - j142 Ω—slightly different from the datasheet values but within acceptable limits.
The discrepancies can be attributed to several factors, including chip variability, minor adjustments in the stub position, and potential deviations in the transmission line impedance. However, these errors can be minimized through multiple measurements and careful calibration.
This paper presents a practical and accurate method for testing the impedance of UHF passive RFID chips under low power conditions. The method not only simplifies the testing process but also enhances accuracy, making it suitable for multi-frequency point testing. Furthermore, the use of a balun improves the reliability of the test setup. This approach addresses the limitations of traditional methods and provides a solid foundation for future impedance testing in higher frequency bands.
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