A wideband digital receiver with uniform channelization and 50% coverage is proposed and implemented using multiple filter bank theory and the FFT method. This system divides the entire sampling frequency band into several parallel channels, enabling full probability interception of signals. It serves as an ideal front-end for detecting frequency-hopping, burst, and adaptive communication signals. The design is primarily used in software-defined radio and electronic warfare applications. The paper discusses the channelization principle, software simulation, and hardware implementation of the wideband digital receiver, while also addressing the design of algorithms, programs, and hardware platforms to meet practical engineering requirements. A digital channelization system with 8 channels operating in the 0–100 MHz frequency range has been successfully realized.
In modern electronic warfare environments, signals are dense and complex, with wider and wider occupied spectra, placing higher demands on the accurate reception of signals by wideband digital channelized receivers. Traditional digital receivers may have dead zones between adjacent channels, potentially leading to signal loss. The improved channel-free polyphase filter eliminates these issues by removing the constraints of equal channel numbers and extraction multiples, which often have a proportional relationship. With their inherent structure, high-speed data processing capabilities, and large number of multipliers, memories, and logic units, FPGAs have become essential tools for signal processing, offering significant advantages in designing high-speed digital filters.
**1. Principle of Digital Channelization**
The input signal x[n] is the digitized output from an ADC. In this digital receiver, each bandpass filter is derived from a prototype low-pass filter hâ‚€[n]. If hâ‚€[n] is a real, causal low-pass filter of length N, then hâ‚€[n] = {h[0], h[1], ..., h[N-1]}. This low-pass filter can be transformed into a series of bandpass filters. The center frequency of the k-th channel is given by:
$$ f_k = \frac{f_s}{2K} \cdot (2k + 1) $$
For a typical digital receiver, the length N of the prototype low-pass filter is greater than the number of channels K. If N = KP, then:
$$ H_k(e^{j\omega}) = H_0\left(e^{j(\omega - \frac{2\pi k}{K})}\right) $$
After the digital channelization process, the frequency is reduced to 1/M of the original, allowing for M-time downsampling.
Digital channelization involves a filter bank consisting of a low-pass filter and several bandpass filters. However, directly sending the ADC signal to each filter results in high computational complexity, making it difficult to implement on hardware. Therefore, the polyphase filtering technique is employed. First, the signal rate is reduced through downsampling, followed by processing in a polyphase filter bank. The specific process is illustrated in Figure 1.
The structure of the multi-filter is generally defined by K = FM, where K is the total number of channels, and M is the downsampling factor. Let hâ‚€[n] be the prototype low-pass filter, which can be decomposed into K-phase components.
$$ h_{0,n}(m) = h_0(n + mK) $$
The hardware implementation block diagram for F=2 is shown in Figure 2.
**2. Matlab Simulation of the System**
First, we must design a prototype low-pass filter. MATLAB is a powerful tool widely used in engineering, signal processing, and mathematics. The firpmord function in MATLAB uses the best approximation maximum and minimum criteria to determine the order of the prototype low-pass filter, while the firpm function is used to calculate the filter coefficients. Assuming a sampling rate of 200 MHz and 16 uniform channels, the passband cutoff frequency is 6.25 MHz, and the stopband cutoff frequency is 12.5 MHz. The filter specifications include a passband gain of 1, a stopband gain of 0, a passband ripple of 0.01 dB, a stopband attenuation of 60 dB, and a sampling rate of 200 MHz.
Based on these parameters, a 96th-order FIR filter is obtained. The characteristics of the FIR filter are shown in Figure 3. Since FPGA implementations require quantized filters, the 10-bit quantized response of the FIR filter is presented in Figure 4.
A 16-times decimation is performed on the prototype low-pass filter, and the multi-phase components are obtained through interpolation twice. The digital channelization process based on the polyphase filter is simulated in the MATLAB environment, and the result is shown in Figure 5. As seen in Figure 5, the 25.1 MHz signal is located in the second channel, and the simulation results indicate that the output amplitude of the second channel is significantly larger—over 60 dB higher than other channels.
**3. Hardware Platform of the Channelized Receiver**
**3.1 Hardware System**
The vector signal source (Jung Jin SG-1710) generates a signal in the 0–200 MHz range, which passes through a transformer and enters the ADC. The ADC outputs LVDS data and a synchronous clock to the FPGA. A voltage-controlled oscillator generates a 200 MHz differential clock for the ADC. The ADC selected is the LTC2242-10, a 10-bit, 250 MSPS, high-IF sampling analog-to-digital converter from Linear Technology, offering a 1.2 GHz analog input bandwidth and requiring 2.5V of power supply. The FPGA used is the EP2S60F484 from Altera’s Stratix II series, grade C5. The voltage-controlled oscillator is the AD9516-3, which provides multi-output clock distribution with sub-picosecond jitter performance, along with an integrated PLL and VCO. The AD9516-3 provides four LVDS outputs at 800 MHz, one of which drives the ADC at 200 MHz. The system hardware block diagram is shown in Figure 6.
**3.2 Hardware System Implementation**
The system was implemented using the described hardware components, with careful attention paid to synchronization, signal integrity, and timing. The FPGA was programmed to handle the polyphase filtering and downsampling processes, ensuring accurate channelization of the input signal. The system demonstrated stable operation and met the expected performance metrics, validating the effectiveness of the design approach.
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