New platform technology design of intelligent microgrid protection device

As the scale of the power grid continues to expand, the power system has gradually increased the requirements for power quality and reliability. A number of power outages with a wide range of impacts have occurred worldwide, exposing the contradiction between distributed power sources and large power grids in ultra-large-scale power systems. The emergence of micro-grid can solve the problem that distributed power grids bring to the large power grid. It usually operates as a distributed power source and a large grid, but when a fault occurs, the micro-grid can be operated on an isolated island and disconnected from the problematic main network. Independently supplies power to the load.

Intelligent micro-grid is realized through integrated communication system, advanced analysis technology and advanced control technology. The microgrid protection should adopt the wide-area protection mode, which consists of a central unit and a local unit. The central unit installed in the main control room of the microgrid can provide full station protection, and the local processing unit is installed at each switch to complete the collection of AC and switching quantities.

For the intelligent micro-network protection mode, a large amount of data is collected into the central unit for summary calculation, and the data at the same time must be processed in the same sampling period without being delayed. Complex control principles and protection technologies that require fast response communication mechanisms require a strong hardware platform.

The traditional protection device for a single object of a line or transformer can no longer meet the wide-area protection mode. The new-generation platform has higher requirements for computing and communication capabilities, and also proposes the applicability of different small systems. The need for ease of use. The system design proposed in this paper can be widely applied to intelligent microgrid protection devices and has practical operability.

1. Design principles

The design principles of the new platform for intelligent microgrid protection devices are as follows:

1.1 Wide Area Protection Scheme

In the wide-area protection scheme, the primary protection is the intelligent micro-network protection central unit, which completes the line and bus protection in the micro-network area. The logical calculation of the primary protection is derived from the data sent by the local unit, and sends a control command to the local unit according to the calculated result. The intelligent terminal mainly completes the local switch information, the collection of the AC quantity, and the execution of the control commands issued by the central unit.

There are many protection modules for intelligent micro-grid, and the number of settings is large. The number of digital input, analog input and digital output is much larger than that of a common protection device. Therefore, the processing capacity and communication transmission of the central unit are protected. Both capacity and data storage capabilities raise high specification requirements.

Compared with the solution that completes the complete protection function by multiple devices, this paper proposes a system design scheme that completes the complete protection function of a single 8U device. This can make the data more centralized, more efficient, lower cost, and also eliminate the complicated work of group screens and wiring, which is conducive to debugging and maintenance work.

1.2 main processor selection

The main processor uses Freescale's 45nm QorIQ family of P2020s with excellent single-threaded performance-to-power ratio for a wide range of applications in the networking, telecom, military and industrial markets. The communications processor features two high-performance Power Architecture e500 cores, each operating at 1.33GHz, with 32KBL1 cache, 512KBL2 cache, 32/64-bit DDR2 and DDR3, and error-correcting code.

The P2020 is rich in peripherals with four SerDes up to 3.125GHz, two PCI Express interfaces, two SerialRapidIO interfaces, two SGMII interfaces, and two high-speed USB controllers. As the core of the main protection, this processor provides a powerful hardware platform, especially suitable for high communication and large-scale data processing, providing sufficient resource guarantee for intelligent micro-network protection, and reserved for future expansion. There is a large room for improvement.

1.3 Data bus design

The total amount of GOOSE and SV data processed by the intelligent micro-network protection is huge, but the amount of data processed by different small systems is different, and different numbers of plug-ins need to be configured according to requirements. The data collected by each plug-in is sent from the data bus to the host processor through the same interface, which requires the data bus to have high-speed, shared, configurable features. Whether used in digital substations or traditional substations, smart plug-ins on the data bus require flexible configuration and scalability.

The data bus is composed of FPGA plus MLVDS: FPGA uses Xilinx Spartan-6 series XC6SLX25T chip, which integrates 24,051 logic units, 936Kbits of RAM blocks, and 38 DSP48A1 units, built-in 1 channel PCI-E hard core The MLVDS chip uses TI's SN65MLVD080 chip to provide an 8-way half-duplex 250Mbit physical channel [3].

Each plug-in is equipped with FPGA and MLVDS chip, FPGA performs data encoding and decoding work, SN65MLVD080 is a bus-based physical channel formed on the bus board, and the data of the main processor and GOOSE and SV plug-in are transmitted to each other. Such a hardware platform design enhances the adaptability of protection and has high redundancy.

1.4 Software and hardware reliability design

Reliability is considered in both hardware and software to ensure proper operation of the device. The software mainly monitors key circuits and core devices, including: open, open readback, power status monitoring, A/D reference judgment, memory (RAM) and custom area (EEPROM) positive and negative code CRC check Wait. If any problem is found, the exit relay will be blocked immediately, an alarm signal will be sent, and an event record will be sent.

The hardware aspect is guaranteed by the choice of the device and the dual configuration of the loop: all designs use industrial-grade devices, and fully consider the derating application, reduce its heat and power consumption, control the failure rate of components, and extend its effective life. cycle. The dual power supply, double sampling and other redundant design prevents the failure of the critical circuit from affecting the overall operation. The dual CPU interlocking outlet circuit reduces the malfunction caused by the failure of a single component.

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