Clock synchronization technology in transmission systems
The synchronization module is the heart of every system, feeding the correct clock signal to every other module in the system. Therefore, special attention needs to be paid to the design and implementation of the synchronization module. This paper investigates the clock characteristics that affect system design and evaluates the causes of signal degradation. The paper also analyzes the impact of synchronization degradation and discusses the standard requirements established by standardization organizations to ensure transmission quality and interoperability of various transmission equipment.
Summary:
Network synchronization and clock generation are important aspects of high-speed transmission system design. In order to improve network efficiency by reducing transmit and receive errors, the quality of the clocks used at various stages of the system must be maintained at a particular level. The network standard defines the architecture of the synchronous network and its expected performance on standard interfaces to ensure seamless integration of transmission quality and transmission equipment. There are a large number of synchronization issues that system designers must be very clear when building a system architecture. This article discusses various sources of clock degradation, such as jitter and drift. This paper also discusses the causes and effects of clock degradation in the transmission system, and analyzes the standard requirements, and proposes various implementation techniques.
Basic Concepts: Jitter and Drift <br> The general definition of jitter can be "a short deviation of an event from its ideal." In digital transmission systems, jitter is defined as the temporal variation of the important moment of a digital signal from its ideal position in time. The important moment can be the optimal sampling moment of a bit stream with a period of T1. Although it is desirable for each bit to appear at an integer multiple of T, it will actually be different. This pulse position modulation is considered to be a type of jitter. This is also known as the phase noise of digital signals. In the figure below, the actual signal edges move periodically around the ideal signal edge, demonstrating the concept of periodic jitter.
Figure 1. Jittering
Jitter, unlike phase noise, is expressed in units of unit intervals (UI). A unit interval is equivalent to one signal period (T) equal to 360 degrees. Suppose the event is E and the nth occurrence is expressed as tE[n]. Then the instantaneous jitter can be expressed as:
A set of peak-to-peak jitter values ​​including N jitter measurements are calculated using minimum and maximum instantaneous jitter measurements as follows:
Drift is low frequency jitter. The typical dividing point between the two is 10 Hz. The effects of jitter and drift can manifest in different but specific areas of the transmission system.
Jitter type <br> Depending on the cause, jitter can be divided into two main types: random jitter and deterministic jitter. Random jitter, as its name suggests, is unpredictable and is caused by random noise effects such as thermal noise. Random jitter typically occurs during edge transitions of digital signals, causing random interval crossings. There is no doubt that random jitter has a Gaussian probability density function (PDF), determined by its mean (μ) and root mean square (rms) (σ). Since the tail of the Gaussian function extends infinitely on both sides of the mean, the instantaneous jitter and peak-to-peak jitter can be infinite. Therefore, random jitter is usually represented and measured by its root mean square value.
Figure 2. Random jitter represented by a Gaussian probability density function
For jitter margins, peak-to-peak jitter is more useful than rms jitter, so the rms value of random jitter needs to be converted to peak-to-peak. To convert the rms jitter into peak-to-peak jitter, an arbitrary limit of the random jitter Gaussian function is defined. The bit error rate (BER) is a useful parameter in this conversion, assuming that the instantaneous jitter in the Gaussian function will be out of error once it falls outside its mandatory limit. The rms jitter to peak-to-peak jitter can be obtained by the following two formulas. 3
The following table is obtained by the formula, and the peak-to-peak jitter in the table corresponds to different BER values.
Deterministic jitter is bounded and therefore predictable and has a defined amplitude limit. Considering integrated circuit (IC) systems, there are a large number of process, device, and system level factors that will affect deterministic jitter. Duty Cycle Distortion (DCD) and Pulse Width Distortion (PWD) can cause distortion of the digital signal, causing the zero-crossing interval to deviate from the ideal position and move up or down. These distortions are usually caused by different timings between the rising and falling edges of the signal. This distortion can also occur if there is ground potential drift in the unbalanced system, voltage offset between differential inputs, changes in signal rise and fall times, and so on.
Figure 3. Dual mode representation of total jitter
Data-dependent jitter (DDJ) and inter-symbol interference (ISI) cause signals to have different zero-crossing interval levels, resulting in different signal transitions for each unique bit pattern. This is also known as mode dependent jitter (PDJ). The low frequency cutoff point and high frequency bandwidth of the signal path will affect the DDJ. When the bandwidth of the signal path can be compared to the bandwidth of the signal, the bits extend into adjacent bit times, causing intersymbol interference (ISI). The low frequency cutoff point will distort the signal of the low frequency device, and the high frequency bandwidth limitation of the system will degrade the performance of the high frequency device. 7
Sinusoidal jitter modulates the signal edges in a sinusoidal mode. This may be due to power supplies to the entire system or even other oscillations in the system. Ground bounce and other power supply variations can also cause sinusoidal jitter. Sinusoidal jitter is widely used for testing and simulation of jitter environments. Uncorrelated jitter can be caused by power supply noise or crosstalk and other electromagnetic interference.
When considering the effect of jitter on digital signals, the entire deterministic jitter and random jitter need to be taken into account. The aggregated result of deterministic jitter and random jitter will yield another probability distribution 4: a two-mode response, with the part representing deterministic jitter and the tail being a Gaussian response representing the random jitter component.
Jitter measurement - TIE, MITE and TEDV
Time Interval Error (TIE) is obtained by measuring the actual clock interval and measuring the same interval of the ideal reference clock. At a given time t, a clock of time T(t) is generated at a time interval called the observation interval, and its TIE with respect to the clock Tref(t) can be expressed by the following formula. (x(t) is called the error function.)
TIE represents the high-frequency phase noise in the signal, providing direct information that the actual clock deviates from the ideal for each cycle. TIE is used to calculate a large number of statistical derived functions such as MTIE, TDEV, and so on.
The Maximum Time Interval Error (MTIE) is defined as the maximum peak-to-peak delay variation of a given clock signal relative to an ideal clock signal over an observation time (t = nt0), where all observation times for that length are measured Within the period (T). Estimate using the following formula:
MTIE is defined for time ramping or drifting. When it is necessary to analyze the long-term characteristics of the clock, it is necessary to measure the MTIE. The MTIE value is a measure of the long-term stability of a clock signal.
Figure 4. Graphical representation of TIE
TDEV is another statistical parameter that measures the expected change in time of a signal as a function of integration time. The DEV can also provide information about the spectral phase (time) noise spectral components. The standard deviation of each point in the TIE graph is calculated for an observation interval that slid over the entire measurement time. This value is averaged over the above measurement time to obtain the TDEV value for that particular interval. Increase the observation interval and repeat the measurement process. TDEV is a measure of short-term stability and is useful when evaluating clock oscillator performance. TDEV is a unit of time.
Causes of Jitter and Drift in High-Speed ​​Transmission Systems <br> One of the most common clock architectures is to run a low-frequency clock on the standby board to generate a synchronized high-frequency clock on each of the transmission cards. The low frequency clock is multiplied within the integrated circuit or by a discrete PLL to generate a high frequency clock. With a typical PLL multiplier, the phase noise on the clock after multiplier is increased to 20*log(N) power of the original clock phase noise, where N is the multiplication factor. In addition, jitter on the PLL reference clock input will extend the lock time and the high-speed PLL will not even lock when the input jitter is too large. Using a higher speed differential clock on the standby board will provide better jitter performance than using a low speed single-ended clock.
Since the VCO is sensitive to input voltage variations, power supply noise is a major factor in increasing clock jitter. The output clock jitter amplitude is proportional to the power supply noise amplitude, the VCO gain, and inversely proportional to the noise frequency. A power supply or ground bounce due to a drop in resistance due to wire resistance and inductive noise due to wire inductance can have a similar effect on the output clock jitter described above. The power supply is fully filtered on the system board, and decoupling capacitors are provided close to the integrated circuit power supply pins to ensure higher jitter performance of the PLL.
Within the system board, the clock and data are independent of each other, and changes in start-up, hold, and delay times at the transmit and receive ends are critical to high rates. Differences in propagation delay between data and clock paths due to different active components in the data and clock paths, differences in wiring delay between clock paths, differences in wiring delay between data bits, and differences between data and clock paths Load conditions, packet length differences, etc., may cause the above changes. When planning the system jitter margin, changes in different signal paths must be taken into account.
When transmitting over a distance, there is jitter accumulation at many points in the transmitter and receiver. In transmitter physical layer implementations, nonlinear characteristics such as DAC nonlinearity or laser nonlinearity can exacerbate signal distortion. In transmission media and receivers, in addition to external spurious sources (mostly in copper conductors), fiber distortion due to different frequency and modulation effects, due to receiver implementation (mainly bandwidth dependent) and clock extraction circuit implementation The resulting signal-dependent phase deviation will increase the jitter of the signal stream.
Figure 5. MTIE bias from TIE graph
Specific to SDH (Synchronous Digital Series) transmissions, there are a large number of system level events that can cause jitter. In a typical transmission system that maps a PDH (Quasi-Synchronous Digital Hierarchy) branch to an SDH frame and transmits it through the SDH NE (Network Component), before the PDH branch to the SDH's terminal demultiplexer demapping, A re-synchronization of VC (virtual container) occurs at intermediate nodes. A gapped clock is used to map each branch to and from the STM-N frame, emitting pulses corresponding to overhead, fixed fill, and adjustment bits, thus causing mapping jitter. Using the adjustment opportunity to compensate for the frequency offset in the PDF branch can cause latency jitter. There is also a pointer adjustment mechanism for compensating for phase fluctuations between the input VC from the initial NE and the locally generated output STM-N frame. Based on the frequency deviation, the VC moves back and forth in the STM-N frame. This will cause the VC fetch point to see a sudden change in the bitstream, resulting in a type of jitter called pointer jitter. All of the above system level jitters will aggravate the total deterministic jitter.
Although all of the above factors exacerbate the jitter of signal propagation from source to destination, the standard requirement still requires a lower jitter value at the transmission point than the theoretical value. Thus, taking into account clock multiplication, power supply variations, electro-optical-to-electrical conversion, transmission and reception effects, and other distorted signals that cause actual signal degradation, the clock driving the signal at the source will have a relatively low jitter value. .
Effect of Jitter on Transceivers <br> Ideally, digital signals are sampled at the midpoint of two adjacent level shifting points. The reason why jitter causes errors is because it changes the edge transition point of the signal relative to the ideal midpoint. The error may be due to a change in the edge of the signal stream that is too late (0.5 UI later in the time than the ideal midpoint (the unit interval is equivalent to one cycle of the signal)) or too early (0.5 UI earlier in time than the ideal midpoint). When the clock sampling edge misses 0.5UI on either side of the signal stream, a 50% error probability will occur, assuming an average conversion density of 0.5. 7 If deterministic jitter and random jitter are known separately, the above two numbers can be used. A table that correlates the peak-to-peak jitter value to the root mean square jitter value to estimate the bit error rate. The calibration jitter, defined as the short-term variation between the optimal sampling instant of the digital signal and the sampling clock extracted therefrom, can cause the above-mentioned error. For commercial applications, the source clock and source transmit interface jitter specifications will be much lower than 1UI.
The transmit interface jitter specification is typically matched to the input jitter tolerance at the receiver. This is especially true for jitter measurement loop filter cutoff frequencies. For example, in an SDH system, there are two types of jitter measurement bandwidths, one for the wideband measurement filter (f1 to f4) and one for the high-band measurement filter (f3 to f4). The value f1 refers to the narrowest clock cutoff frequency of the output clock signal that can be used in the line system's PLL. Jitter below the frequency of this bandwidth will pass through the system, while higher frequency jitter will be partially absorbed. The value f3 represents the bandwidth of the input clock capture circuit. Jitter above this frequency will cause calibration jitter. Calibration jitter causes loss of optical power and requires additional optical power to prevent various degradations. Therefore, it is important to limit the jitter of the high-band spectrum at the transmitter end.
Impact of Drift on Transceivers <br> Most telecom receivers on the market use a buffer to accommodate random fluctuations in the line signal. Block diagram 6 below shows this concept in detail. The recovery clock feeds the data into a flexible buffer, and the system clock sends the data out to the heart of the device.
In a quasi-synchronous transmission system, the transmitter and receiver operate at mutually independent and very close frequencies, and fL and Fs represent the frequencies of the transmitter and receiver, respectively. When there is a phase or frequency difference between the two, the elastic storage will eliminate it, otherwise the buffer will be underloaded or overflowed (depending on the magnitude of the difference and the size of the elastic buffer), resulting in a controllable frame slip ( Basic rate transfer) or one-bit adjustment (high-order asynchronous multiplexer).
In quasi-synchronous applications, frequency variations and buffer depths are normalized based on acceptable buffer slip. The original network was mainly used for voice transmission, and it did not cause a drop in voice quality under a certain frequency threshold. The change is +/- 50 ppm in the ITU-T specification. But as the network begins to deliver compressed voice, fax format data, video, and other types of media applications, sliding has severely degraded efficiency for errors and retransmissions, as well as the emerging synchronous network.
In synchronous transmission systems, the system clock is typically synchronized to the recovered clock of the interface used to receive higher clock level signals. The instantaneous and cumulative differences in phase and frequency between the recovered clock and the system clock will be absorbed by the elastic buffer, which would otherwise cause the elastic memory to overflow/underload (depending on the buffer size and the magnitude of the change), causing pointer adjustments to be delayed or advanced. Frame transfer, frame slip, or bit adjustment somewhere in the system.
In a synchronous system, all network components operate at the same average frequency, and frame degradation can be eliminated by a pointer mechanism. These pointer mechanisms will advance or delay the position of the payload in the transmission frame, thereby adjusting the frequency and phase variations present in the receive and system clocks. The buffers in the SDH transceiver are smaller than those in the PDH transceiver and have limitations on irregularities such as pointer movement that may result in the SDH system. Therefore, the requirements of the synchronous system are more stringent than those of the PDH system. Due to the history of network development and interoperable connections between different networks, these synchronization networks are connected through a quasi-synchronous network at some stage or at other stages. Therefore, the clock architecture of the PDH network should also be taken into account.
The MTIE provides a peak time variation of the clock relative to a known ideal reference clock. The MTIE value will be used in the design of the elastic buffer of the isochronous transfer and switching device. In elastic storage, the buffer fill level is proportional to the TIE between the input digital signal and the local system clock. Ensuring that the clock complies with the MTIE's clock specifications will ensure that a certain buffer threshold is not exceeded. Therefore, in the buffer design, its size depends on the specified limits of the MTIE.
Figure 6. Receiver interface of a typical transmission system
System Clock Output Phase Disturbance Effects on Transceivers <br> The output phase change of a clock can be obtained by analyzing its MTIE information. Drift generation (in free-running mode and synchronous mode) mainly refers to the long-term stability of the clock oscillator used in the system. In the free-running mode, the stability of the system is only affected by the stability of the oscillator. In addition to drift generation, the output clock phase is also affected by a large number of system irregularities.
Especially for a system synchronizer, switching the reference source from a bad or degraded reference clock to a normal reference clock may result in output phase perturbations. The conventional VCO (Voltage Controlled Oscillator) used in the high-speed PLL for transmission uses a method of switching the capacitor bank when changing the reference clock. This switching transition causes a temporary phase shift in the output clock. This problem can be solved by using an ultra-low jitter clock multiplier circuit.
High-performance network clocks use a mechanism called "hold" when all of the system's reference clocks are lost. This is achieved by the memory storage technology generating the last known good reference clock for the system. Entering and exiting the hold mode may cause phase disturbances to the output. When in the hold mode, the output phase error continues to occur due to the inaccuracy of accurate frequency reproduction. Advances in integrated circuit technology have resulted in retention accuracy of 0.01 ppb. Input reference clock degradation and maintenance tests on the system (which do not cause a reference clock switch) are too small and can cause output phase disturbances.
System output disturbances are limited, depending on the input tolerances that the system can accept at a lower level. For example, for a clock that conforms to G.813 Option 1, the phase slope and maximum phase error allowed in phase perturbations are limited to 1μS, the maximum phase slope is 7.5ppm, two 120ns phase error segments, and the remaining phase slope is 0.05. Ppm. These numbers correspond to the input jitter tolerances specified by the G.825 standard, which describes the control of jitter and wander within the SDH network.
When the output phase is disturbed, keeping the magnitude and rate of the phase error within the limits recommended by the standards organization ensures proper signal degradation in the end-to-end system to avoid data corruption or loss. For example, when the system synchronizer performs a reference clock switch, if the output phase error is within the specification, the synchronizer can implement an "uninterrupted" reference clock switch, indicating that there is a buffer overflow or underload, causing pointer movement, bit adjustment. Or slide.
Conclusion <br> Network synchronization and clock generation are the most important parts of any high-speed transmission network system. This article discusses the different types of clock degradation, mainly jitter and drift. The article also details the causes of the above deterioration and how they affect the transmission system. The systematic design and implementation of the clock subsystem will improve the performance of the entire system, reduce the bit error rate, and be easy to integrate, providing higher transmission quality and efficiency.
Summary:
Network synchronization and clock generation are important aspects of high-speed transmission system design. In order to improve network efficiency by reducing transmit and receive errors, the quality of the clocks used at various stages of the system must be maintained at a particular level. The network standard defines the architecture of the synchronous network and its expected performance on standard interfaces to ensure seamless integration of transmission quality and transmission equipment. There are a large number of synchronization issues that system designers must be very clear when building a system architecture. This article discusses various sources of clock degradation, such as jitter and drift. This paper also discusses the causes and effects of clock degradation in the transmission system, and analyzes the standard requirements, and proposes various implementation techniques.
Basic Concepts: Jitter and Drift <br> The general definition of jitter can be "a short deviation of an event from its ideal." In digital transmission systems, jitter is defined as the temporal variation of the important moment of a digital signal from its ideal position in time. The important moment can be the optimal sampling moment of a bit stream with a period of T1. Although it is desirable for each bit to appear at an integer multiple of T, it will actually be different. This pulse position modulation is considered to be a type of jitter. This is also known as the phase noise of digital signals. In the figure below, the actual signal edges move periodically around the ideal signal edge, demonstrating the concept of periodic jitter.
Figure 1. Jittering
Jitter, unlike phase noise, is expressed in units of unit intervals (UI). A unit interval is equivalent to one signal period (T) equal to 360 degrees. Suppose the event is E and the nth occurrence is expressed as tE[n]. Then the instantaneous jitter can be expressed as:
A set of peak-to-peak jitter values ​​including N jitter measurements are calculated using minimum and maximum instantaneous jitter measurements as follows:
Drift is low frequency jitter. The typical dividing point between the two is 10 Hz. The effects of jitter and drift can manifest in different but specific areas of the transmission system.
Jitter type <br> Depending on the cause, jitter can be divided into two main types: random jitter and deterministic jitter. Random jitter, as its name suggests, is unpredictable and is caused by random noise effects such as thermal noise. Random jitter typically occurs during edge transitions of digital signals, causing random interval crossings. There is no doubt that random jitter has a Gaussian probability density function (PDF), determined by its mean (μ) and root mean square (rms) (σ). Since the tail of the Gaussian function extends infinitely on both sides of the mean, the instantaneous jitter and peak-to-peak jitter can be infinite. Therefore, random jitter is usually represented and measured by its root mean square value.
Figure 2. Random jitter represented by a Gaussian probability density function
For jitter margins, peak-to-peak jitter is more useful than rms jitter, so the rms value of random jitter needs to be converted to peak-to-peak. To convert the rms jitter into peak-to-peak jitter, an arbitrary limit of the random jitter Gaussian function is defined. The bit error rate (BER) is a useful parameter in this conversion, assuming that the instantaneous jitter in the Gaussian function will be out of error once it falls outside its mandatory limit. The rms jitter to peak-to-peak jitter can be obtained by the following two formulas. 3
The following table is obtained by the formula, and the peak-to-peak jitter in the table corresponds to different BER values.
Deterministic jitter is bounded and therefore predictable and has a defined amplitude limit. Considering integrated circuit (IC) systems, there are a large number of process, device, and system level factors that will affect deterministic jitter. Duty Cycle Distortion (DCD) and Pulse Width Distortion (PWD) can cause distortion of the digital signal, causing the zero-crossing interval to deviate from the ideal position and move up or down. These distortions are usually caused by different timings between the rising and falling edges of the signal. This distortion can also occur if there is ground potential drift in the unbalanced system, voltage offset between differential inputs, changes in signal rise and fall times, and so on.
Figure 3. Dual mode representation of total jitter
Data-dependent jitter (DDJ) and inter-symbol interference (ISI) cause signals to have different zero-crossing interval levels, resulting in different signal transitions for each unique bit pattern. This is also known as mode dependent jitter (PDJ). The low frequency cutoff point and high frequency bandwidth of the signal path will affect the DDJ. When the bandwidth of the signal path can be compared to the bandwidth of the signal, the bits extend into adjacent bit times, causing intersymbol interference (ISI). The low frequency cutoff point will distort the signal of the low frequency device, and the high frequency bandwidth limitation of the system will degrade the performance of the high frequency device. 7
Sinusoidal jitter modulates the signal edges in a sinusoidal mode. This may be due to power supplies to the entire system or even other oscillations in the system. Ground bounce and other power supply variations can also cause sinusoidal jitter. Sinusoidal jitter is widely used for testing and simulation of jitter environments. Uncorrelated jitter can be caused by power supply noise or crosstalk and other electromagnetic interference.
When considering the effect of jitter on digital signals, the entire deterministic jitter and random jitter need to be taken into account. The aggregated result of deterministic jitter and random jitter will yield another probability distribution 4: a two-mode response, with the part representing deterministic jitter and the tail being a Gaussian response representing the random jitter component.
Jitter measurement - TIE, MITE and TEDV
Time Interval Error (TIE) is obtained by measuring the actual clock interval and measuring the same interval of the ideal reference clock. At a given time t, a clock of time T(t) is generated at a time interval called the observation interval, and its TIE with respect to the clock Tref(t) can be expressed by the following formula. (x(t) is called the error function.)
TIE represents the high-frequency phase noise in the signal, providing direct information that the actual clock deviates from the ideal for each cycle. TIE is used to calculate a large number of statistical derived functions such as MTIE, TDEV, and so on.
The Maximum Time Interval Error (MTIE) is defined as the maximum peak-to-peak delay variation of a given clock signal relative to an ideal clock signal over an observation time (t = nt0), where all observation times for that length are measured Within the period (T). Estimate using the following formula:
MTIE is defined for time ramping or drifting. When it is necessary to analyze the long-term characteristics of the clock, it is necessary to measure the MTIE. The MTIE value is a measure of the long-term stability of a clock signal.
Figure 4. Graphical representation of TIE
TDEV is another statistical parameter that measures the expected change in time of a signal as a function of integration time. The DEV can also provide information about the spectral phase (time) noise spectral components. The standard deviation of each point in the TIE graph is calculated for an observation interval that slid over the entire measurement time. This value is averaged over the above measurement time to obtain the TDEV value for that particular interval. Increase the observation interval and repeat the measurement process. TDEV is a measure of short-term stability and is useful when evaluating clock oscillator performance. TDEV is a unit of time.
Causes of Jitter and Drift in High-Speed ​​Transmission Systems <br> One of the most common clock architectures is to run a low-frequency clock on the standby board to generate a synchronized high-frequency clock on each of the transmission cards. The low frequency clock is multiplied within the integrated circuit or by a discrete PLL to generate a high frequency clock. With a typical PLL multiplier, the phase noise on the clock after multiplier is increased to 20*log(N) power of the original clock phase noise, where N is the multiplication factor. In addition, jitter on the PLL reference clock input will extend the lock time and the high-speed PLL will not even lock when the input jitter is too large. Using a higher speed differential clock on the standby board will provide better jitter performance than using a low speed single-ended clock.
Since the VCO is sensitive to input voltage variations, power supply noise is a major factor in increasing clock jitter. The output clock jitter amplitude is proportional to the power supply noise amplitude, the VCO gain, and inversely proportional to the noise frequency. A power supply or ground bounce due to a drop in resistance due to wire resistance and inductive noise due to wire inductance can have a similar effect on the output clock jitter described above. The power supply is fully filtered on the system board, and decoupling capacitors are provided close to the integrated circuit power supply pins to ensure higher jitter performance of the PLL.
Within the system board, the clock and data are independent of each other, and changes in start-up, hold, and delay times at the transmit and receive ends are critical to high rates. Differences in propagation delay between data and clock paths due to different active components in the data and clock paths, differences in wiring delay between clock paths, differences in wiring delay between data bits, and differences between data and clock paths Load conditions, packet length differences, etc., may cause the above changes. When planning the system jitter margin, changes in different signal paths must be taken into account.
When transmitting over a distance, there is jitter accumulation at many points in the transmitter and receiver. In transmitter physical layer implementations, nonlinear characteristics such as DAC nonlinearity or laser nonlinearity can exacerbate signal distortion. In transmission media and receivers, in addition to external spurious sources (mostly in copper conductors), fiber distortion due to different frequency and modulation effects, due to receiver implementation (mainly bandwidth dependent) and clock extraction circuit implementation The resulting signal-dependent phase deviation will increase the jitter of the signal stream.
Figure 5. MTIE bias from TIE graph
Specific to SDH (Synchronous Digital Series) transmissions, there are a large number of system level events that can cause jitter. In a typical transmission system that maps a PDH (Quasi-Synchronous Digital Hierarchy) branch to an SDH frame and transmits it through the SDH NE (Network Component), before the PDH branch to the SDH's terminal demultiplexer demapping, A re-synchronization of VC (virtual container) occurs at intermediate nodes. A gapped clock is used to map each branch to and from the STM-N frame, emitting pulses corresponding to overhead, fixed fill, and adjustment bits, thus causing mapping jitter. Using the adjustment opportunity to compensate for the frequency offset in the PDF branch can cause latency jitter. There is also a pointer adjustment mechanism for compensating for phase fluctuations between the input VC from the initial NE and the locally generated output STM-N frame. Based on the frequency deviation, the VC moves back and forth in the STM-N frame. This will cause the VC fetch point to see a sudden change in the bitstream, resulting in a type of jitter called pointer jitter. All of the above system level jitters will aggravate the total deterministic jitter.
Although all of the above factors exacerbate the jitter of signal propagation from source to destination, the standard requirement still requires a lower jitter value at the transmission point than the theoretical value. Thus, taking into account clock multiplication, power supply variations, electro-optical-to-electrical conversion, transmission and reception effects, and other distorted signals that cause actual signal degradation, the clock driving the signal at the source will have a relatively low jitter value. .
Effect of Jitter on Transceivers <br> Ideally, digital signals are sampled at the midpoint of two adjacent level shifting points. The reason why jitter causes errors is because it changes the edge transition point of the signal relative to the ideal midpoint. The error may be due to a change in the edge of the signal stream that is too late (0.5 UI later in the time than the ideal midpoint (the unit interval is equivalent to one cycle of the signal)) or too early (0.5 UI earlier in time than the ideal midpoint). When the clock sampling edge misses 0.5UI on either side of the signal stream, a 50% error probability will occur, assuming an average conversion density of 0.5. 7 If deterministic jitter and random jitter are known separately, the above two numbers can be used. A table that correlates the peak-to-peak jitter value to the root mean square jitter value to estimate the bit error rate. The calibration jitter, defined as the short-term variation between the optimal sampling instant of the digital signal and the sampling clock extracted therefrom, can cause the above-mentioned error. For commercial applications, the source clock and source transmit interface jitter specifications will be much lower than 1UI.
The transmit interface jitter specification is typically matched to the input jitter tolerance at the receiver. This is especially true for jitter measurement loop filter cutoff frequencies. For example, in an SDH system, there are two types of jitter measurement bandwidths, one for the wideband measurement filter (f1 to f4) and one for the high-band measurement filter (f3 to f4). The value f1 refers to the narrowest clock cutoff frequency of the output clock signal that can be used in the line system's PLL. Jitter below the frequency of this bandwidth will pass through the system, while higher frequency jitter will be partially absorbed. The value f3 represents the bandwidth of the input clock capture circuit. Jitter above this frequency will cause calibration jitter. Calibration jitter causes loss of optical power and requires additional optical power to prevent various degradations. Therefore, it is important to limit the jitter of the high-band spectrum at the transmitter end.
Impact of Drift on Transceivers <br> Most telecom receivers on the market use a buffer to accommodate random fluctuations in the line signal. Block diagram 6 below shows this concept in detail. The recovery clock feeds the data into a flexible buffer, and the system clock sends the data out to the heart of the device.
In a quasi-synchronous transmission system, the transmitter and receiver operate at mutually independent and very close frequencies, and fL and Fs represent the frequencies of the transmitter and receiver, respectively. When there is a phase or frequency difference between the two, the elastic storage will eliminate it, otherwise the buffer will be underloaded or overflowed (depending on the magnitude of the difference and the size of the elastic buffer), resulting in a controllable frame slip ( Basic rate transfer) or one-bit adjustment (high-order asynchronous multiplexer).
In quasi-synchronous applications, frequency variations and buffer depths are normalized based on acceptable buffer slip. The original network was mainly used for voice transmission, and it did not cause a drop in voice quality under a certain frequency threshold. The change is +/- 50 ppm in the ITU-T specification. But as the network begins to deliver compressed voice, fax format data, video, and other types of media applications, sliding has severely degraded efficiency for errors and retransmissions, as well as the emerging synchronous network.
In synchronous transmission systems, the system clock is typically synchronized to the recovered clock of the interface used to receive higher clock level signals. The instantaneous and cumulative differences in phase and frequency between the recovered clock and the system clock will be absorbed by the elastic buffer, which would otherwise cause the elastic memory to overflow/underload (depending on the buffer size and the magnitude of the change), causing pointer adjustments to be delayed or advanced. Frame transfer, frame slip, or bit adjustment somewhere in the system.
In a synchronous system, all network components operate at the same average frequency, and frame degradation can be eliminated by a pointer mechanism. These pointer mechanisms will advance or delay the position of the payload in the transmission frame, thereby adjusting the frequency and phase variations present in the receive and system clocks. The buffers in the SDH transceiver are smaller than those in the PDH transceiver and have limitations on irregularities such as pointer movement that may result in the SDH system. Therefore, the requirements of the synchronous system are more stringent than those of the PDH system. Due to the history of network development and interoperable connections between different networks, these synchronization networks are connected through a quasi-synchronous network at some stage or at other stages. Therefore, the clock architecture of the PDH network should also be taken into account.
The MTIE provides a peak time variation of the clock relative to a known ideal reference clock. The MTIE value will be used in the design of the elastic buffer of the isochronous transfer and switching device. In elastic storage, the buffer fill level is proportional to the TIE between the input digital signal and the local system clock. Ensuring that the clock complies with the MTIE's clock specifications will ensure that a certain buffer threshold is not exceeded. Therefore, in the buffer design, its size depends on the specified limits of the MTIE.
Figure 6. Receiver interface of a typical transmission system
System Clock Output Phase Disturbance Effects on Transceivers <br> The output phase change of a clock can be obtained by analyzing its MTIE information. Drift generation (in free-running mode and synchronous mode) mainly refers to the long-term stability of the clock oscillator used in the system. In the free-running mode, the stability of the system is only affected by the stability of the oscillator. In addition to drift generation, the output clock phase is also affected by a large number of system irregularities.
Especially for a system synchronizer, switching the reference source from a bad or degraded reference clock to a normal reference clock may result in output phase perturbations. The conventional VCO (Voltage Controlled Oscillator) used in the high-speed PLL for transmission uses a method of switching the capacitor bank when changing the reference clock. This switching transition causes a temporary phase shift in the output clock. This problem can be solved by using an ultra-low jitter clock multiplier circuit.
High-performance network clocks use a mechanism called "hold" when all of the system's reference clocks are lost. This is achieved by the memory storage technology generating the last known good reference clock for the system. Entering and exiting the hold mode may cause phase disturbances to the output. When in the hold mode, the output phase error continues to occur due to the inaccuracy of accurate frequency reproduction. Advances in integrated circuit technology have resulted in retention accuracy of 0.01 ppb. Input reference clock degradation and maintenance tests on the system (which do not cause a reference clock switch) are too small and can cause output phase disturbances.
System output disturbances are limited, depending on the input tolerances that the system can accept at a lower level. For example, for a clock that conforms to G.813 Option 1, the phase slope and maximum phase error allowed in phase perturbations are limited to 1μS, the maximum phase slope is 7.5ppm, two 120ns phase error segments, and the remaining phase slope is 0.05. Ppm. These numbers correspond to the input jitter tolerances specified by the G.825 standard, which describes the control of jitter and wander within the SDH network.
When the output phase is disturbed, keeping the magnitude and rate of the phase error within the limits recommended by the standards organization ensures proper signal degradation in the end-to-end system to avoid data corruption or loss. For example, when the system synchronizer performs a reference clock switch, if the output phase error is within the specification, the synchronizer can implement an "uninterrupted" reference clock switch, indicating that there is a buffer overflow or underload, causing pointer movement, bit adjustment. Or slide.
Conclusion <br> Network synchronization and clock generation are the most important parts of any high-speed transmission network system. This article discusses the different types of clock degradation, mainly jitter and drift. The article also details the causes of the above deterioration and how they affect the transmission system. The systematic design and implementation of the clock subsystem will improve the performance of the entire system, reduce the bit error rate, and be easy to integrate, providing higher transmission quality and efficiency.
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