14-bit 125Msps analog-to-digital converter ADS5500 and its application

Pick    To: This paper introduces the performance characteristics and design considerations of the ADS5500 , and briefly describes its application in video signal processing.

Overview

In recent years, with the rapid development of digital signal processing technology and the emergence of new theories and new algorithms, combined with the overall improvement of the performance of digital signal processing devices, the actual system requirements for analog-to-digital converters are getting higher and higher. Therefore, in practical applications, it is generally required that the analog-to-digital converter must have both high sampling rate and accuracy, a large dynamic range, an extremely wide frequency response range, and a flexible digital interface.

The ADS5500 is a high-performance analog-to-digital converter with a 14 -bit resolution and 125 MSPS sampling rate developed by TI . The chip is available in a 64- pin TQFP PowerPAD package. To achieve higher system integration, it also includes a full conversion solution with wide bandwidth linear sample / hold and internal reference. At 100MHz , the ADS5500 has a signal-to-noise ratio (SNR) of 70dB , a distortion-free dynamic range (SFDR) of 82dB , a differential input voltage of 2.2Vpp , an operating voltage of 3.3V ( unipolar ) , and a power consumption of only 750mW . The internal reference simplifies system design and the parallel CMOS- compatible data output interface ensures seamless connection to common logic and facilitates connection to digital signal processors. Its internal structure is shown in Figure 1 .

Figure 1   Internal block diagram of the ADS5500

Figure 2   ADS5500 working signal timing

Figure 3   Analog input section

Design considerations

The ADS5500 is a low-power, 125-PSPS , 14 -bit pipelined analog-to-digital converter that requires only a single 3.3V unipolar supply. The data conversion process starts on the rising edge of the clock signal waveform. Once the analog signal is captured by the sample / hold portion of the converter, the sampling process of the input signal is sequentially divided into a series of pipeline operations to make the rising edge and falling of the clock signal. Data conversion can be performed along the edge. A delay of 16 clock cycles is required from the input of the analog signal to the output of 14 bits of data . Figure 2 shows the corresponding timing of the ADS5500 input and output signals and the clock waveform.

Input configuration

The analog input portion of the ADS5500 consists primarily of a differential track / hold amplifier and switched capacitor ( Figure 3) .

Differential input technology ensures high performance at high sample rates while also providing very high input bandwidth, which is especially important for some IF sampling or undersampling applications.

A differential input / output amplifier ( such as the OPA695) can be used for the input configuration of the low frequency input signal to simplify the front end driver circuit. The advantage of this configuration is that it has greater flexibility, and the amplifier can be used to perform polarity conversion ( unipolar to differential ) of analog input signals , signal amplification, and front-end pre-filtering of the ADC .

Reference source circuit

The internal reference of the ADS5500 simplifies the circuit layout of the board, and no additional circuitry is available on the board. But from the perspective of optimizing performance considerations, can be connected to a respective capacitor in 1mF REFP and REFM pins and grounded. Further, in order to better set the operating current of the chip, it is also connected to a 47 Ω resistor in the IREF pin, and is connected to pin AGND (FIG. 4).

Figure 4   REFP , REFM, and IREF pins optimize system performance

Figure 5   Clock input signal pin connection circuit

Figure 6 ADS5500 build real-time image processing system

Clock input signal

The clock input signal of the chip can be a unipolar or differential signal. In the normal mode, the voltage amplitude of the clock input signal is set to 1.5V , and the CLKP pin and the CLKM pin are connected to the CM pin through a 5k Ω resistor ( Fig. 5). ) .

From a practical point of view, selecting a low-jitter clock source and performing corresponding band-pass filtering can greatly improve the performance of the high-frequency sampling system. The ADC core inside the chip can perform data conversion on both the rising and falling edges of the clock signal waveform, further improving the working efficiency of the chip. When there is no clock source or the clock frequency is lower than 10MSPS , the chip will automatically switch to sleep mode.

Output options

Chip generates an output signal data of 14 bits (D13-D0), 1 data ready signal (CLKOUT pin) and an indication bit data overflow (OVR pin, the output data when the amplitude exceeds the maximum value, the bit is set For 1) .

The data format of the output signal and the polarity of the clock output signal can be set by changing the DFS pin level. The data format of the output signal has two forms: direct binary code and two's complement code, and the clock polarity is expressed as the output data is valid on the rising or falling edge of the clock waveform. There are four selection ranges for DFS pin levels, so there are four correspondences. Table 1 shows the correspondence between these four modes.

Application examples

Figure 6 is a real-time image processing system. The CCD sensor sends the original image ( analog signal ) to the ADS5500 for high-frequency sampling to obtain a high-precision digital image signal, which is then sent to the image processing unit through the high-speed synchronous FIFO . The processing and compression of the image is completed, and the processed data is displayed on a liquid crystal display or a CRT display.

Conclusion

The ADS5500 interface is simple, easy to use, flexible, 14 -bit sampling accuracy, and has a high conversion speed. In most applications where high-speed data acquisition and high-precision measurements are required, the chip is highly practical.

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