Application and hardware design of VoIP voice card in router

Abstract: This paper introduces the application of VoIP voice card in the router, and describes in detail the hardware structure and working mode of a voice card applied to the router.

Keywords: VoIP PCI FXS router voice compression

1 VoIP application in the router

In recent years, VoIP (Voice over Internet Protocol) has brought a strong impact on the communication market. After the IP voice service was launched, it was widely welcomed because of its outstanding advantages in calling charges over traditional telephones. The application of VoIP technology in routers can greatly reduce the telephone bills of enterprises or organizations that have multiple departments working in different places. Figure 1 shows the application of a VoIP router between the Public Security Bureau and the police station.

The routers DCR-2501V and DCR-2509V of the police station use FR (Frame Relay) or DDN lines to interconnect with the DCR-3660 of the branch office. The computers at each network point can connect to the LAN or Internet of the branch office through the router to realize data communication. The DCR-2501V or DCR-2509V is connected to the ordinary telephone through the FXS voice port, and the branch router is connected to the PBX through the E&M interface, so that data communication between internal departments can be realized, and a zero-cost voice call can be performed at the same time.

The reason why VoIP has a huge advantage in cost is that it utilizes the packetization and digital transmission technology of computer communication. First, the voice data is compressed and encoded according to a certain voice compression standard, and then the data is packaged according to the IP related protocol. The data packet is transmitted to the receiving end through the IP network, and the receiving end serializes the data packets arriving in different orders in their own order, and decodes and decompresses to recover the original voice signal. Compared with traditional voice services, VoIP has drawbacks in terms of time delay and voice quality. Some advanced protocols such as Resource Reservation Protocol (RSVP) and different types of services (Diffserv) can be used to optimize the transmission of voice packets as much as possible to reduce transmission delay and congestion.

Currently, the standards for VoIP are mainly those recommended by the International Telecommunication Union Technology Department (ITU-T). The 323 system and the IETF recommended Session Initiation Protocol (SIP) system. The former mainly implements multimedia service development on the telecommunication network, and the technology has matured. The latter is based on a dynamic Internet model and is a simple signaling protocol for network conferencing and telephony based on softswitch technology. In China, the main choice is H. 323 technical standards to achieve VoIP, in H. In the 323 series of standards, the audio compression coding standard has G. 711, G. 722, G. 723 and G729, etc.

This article describes the hardware design and working principles of a VoIP voice card that has been applied to router products.

2 VoIP voice card hardware structure

The voice card is based on AudioCodes' VoPP (Voice Over Packet Processor) AC48302. It uses a PCI interface to provide two FXS (Foreign Exchange Station) voice/fax interfaces. The VoIP function is implemented in a series of routers developed by the company. The hardware structure block diagram is shown in Figure 2. The following describes the principle and function of each part of the hardware.

2.1 PCI interface

The router main board and the voice card are connected through a PCI bus, which is convenient for general use. The PCI interface chip PLX9030 is used to convert the voice card local bus (HPI) to the PCI bus. Since the data traffic on the voice card is not large, it is not necessary to use the DMA method to actively transfer data to the Memory space on the router motherboard. Therefore, the voice card works in the slave mode of the PCI mode, and the AC48302 receives or transmits voice data through the interrupt mode. The data width and speed of the PCI bus are 32 bits/33 MHz.

2.2 CPLD section

The AC48302 uses an 8-bit parallel main processor interface HPI for data exchange with an external CPU (ie, the router CPU). In this design, the HPI interface is slightly different from the local bus interface timing of the PLX9030 and is adjusted by the CPLD. In addition, the router CPU can also control the CODEC and SLIC chips through the CPLD.

2.3 AC48302 chip

The AC48302 is a low-power, low-cost, dual-channel voice packet processor from AudioCodes that integrates a DSP core. The main features of the chip are as follows:

· Support two channels of voice compression coding, voice compression standards include G. 729A, G. 723.1, G. 727, G. 726, G. 711.

·Compatible with T. 38 or FRF. 11 fax relay (2.4 ~ 14.4kbps).

• Call ID generation and detection, call progress and detection and generation of user defined speech.

·Compatible with G. 256's 25ms echo cancellation.

High performance effective voice detection (VAD) and comfort noise generation (CNG).

DTMF detection and generation.

· A-law/μ-law optional Codec interface with input and output gain control.

· PCM Highway interface.

Parallel Host Processor Interface (HPI).

The hardware interfaces of each part of AC48302 are shown in Figure 3.

Figure 4 AC48302 HPI memory mapping

2.3.1 Voice Interface (Voice Interface)

The voice interface provides input and output channels for uncompressed voice and fax data. The voice interface provides four signal lines to form a PCM bus, and is directly connected to the PCM Highway of the external CODEC chip. The four signal lines are PCMIN, PCMOUT, PCMCLK, and PCMFS. PCMIN inputs the PCM signal sent from the CODEC. The DSP inside the AC48302 is compressed according to the corresponding standard (such as G.729) and then forwarded from the HPI port to the router CPU. PCMOUT, on the other hand, AC48302 decompresses the voice data sent by the router CPU according to the appropriate standard, and then sends it from the PCMOUT port to the external CODEC. The CODEC is converted into a voice signal after digital/analog conversion. The smoke is sent to the user through the user interface. PCMCLK provides a 2.048MHz bit-synchronous clock, while PCMFS provides an 8kHz frame-synchronized clock.

2.3.2 HPI interface

In this design, the router CPU communicates with the AC48302 through the HPI port. The router CPU and DSP implement data interaction through the on-chip shared dual-port memory of the AC48302. The mapping relationship of on-chip shared memory is shown in Figure 4.

The HPI interface includes an 8-bit data bus and several control buses. The router CPU controls the AC48302 and accesses the on-chip memory space through three registers (HPIC, HPIA, and HPID). The HPIC is a control register that selects the high and low byte order, generation and receive interrupts of the AC48302. HPIA is an address register that is used to address the 2K of on-chip memory. The HPID is a data register, which is used to buffer two bytes of data for each read and write. The external CPU can access the HPID in a single Word or block data mode. When accessed in block data mode, the HPIA registers are automatically accumulated, which can reduce the external CPU write. The overhead of the HPIA registers. The internal registers and memory of the AC48302 are 16 bits wide. Therefore, the external CPU must use two bytes as the basic unit for each access to the AC48302. The signal line HI/LO is used to select the high and low bytes. The signals HRS1 and HRS0 indicate which one is currently accessed. register.

In addition to the above two important interfaces, the AC48302 also includes a PCM clock generator, a JTAG interface for testing, and a Memory&I/O interface for accessing external SRAM and processing channel-assisted signaling.

2.4 CODEC interface chip

The CODEC chip is responsible for decoding the PCM data sent by the DSP decompression, and sending the filtered analog voice signal to the subscriber line interface chip SLIC, and the SLIC performs 2-4 line conversion and then sends it to the user end; meanwhile, the CODEC It is also responsible for PCM encoding the analog voice signal sent by the SLIC, and then sending it to the DSP chip for compression processing.

In this design, the CODEC chip uses IDT's 4-channel PCM codec chip IDT821034. The chip has programmable gain settings, main clock options (2.048MHz, 4.096MHz and 8.192MHz), up to 128 programmable time slots, A-law/μ-law optional, built-in digital filter, string Line control interface, low power consumption and other features. In this design, the main clock is 2.048MHz (E1 frame mode), which can be divided into 32 equal time slots (Slot0~Slot31). The receiving and transmitting time slots of 4 channels can be written to the serial control port. Words are dynamically selected. The position of each time slot is referenced to a frame synchronization clock signal of 8 kHz. In IDT821034, the position of time slot 0 relative to the frame synchronization pulse has a delay mode and a non-delay mode (Fig. 6 is a non-delay mode).

The PCM master clock (BCLK), frame sync clock (FS), receive data (DR), and transmit data (DX) together form a PCM Highway signal that is connected to the AC48302. BCLK and FS correspond to PCMCLK and PCMFS of AC48302 respectively. These two clock signals are generated by AC48302; DR and DX correspond to PCMOUT and PCMIN of AC48302 respectively. The relationship between the PCM Highway signal timing and the time slot and the frame synchronization signal is shown in Figures 5 and 6, respectively. In order to correctly send and receive data between the CODEC and the DSP chip, the CODEC chip is generally selected to transmit data DX on the rising edge of BCLK, and the falling edge sampling data DR, while at the other end of the AC48302, the PCMIN is sampled on the falling edge of the clock, and the rising edge sends PCMOUT.

2.5 Subscriber Line Interface (SLIC) chip

In order to enable the voice card to provide FXS interface function, Ericsson's new SLIC chip PBL83710 is used to connect the user interface. It can generate high voltage ringing signal and provide automatic battery feed switching inside the chip. It has loop ringing and ground key detection and 2-4 line conversion. The chip integrates many traditional ringing relays, ringing generators and other devices into one chip, saving board space and cost.

3 VoIP voice card hardware driver process

The hardware driver mainly performs the following functions:

(1) Initialize the PLX9030 chip, configure the relevant registers, and select the local bus mode of operation.

(2) Initialize the AC48302 chip and start the DSP core inside the AC48302 to normal operation. The startup steps of the AC48302 are divided into the following steps in sequence: kernel code (Kernel) download; program code (Program) download; initialization mode; start run.

(3) Drive the normal operation of the voice card. Receiving and processing the off-hook interrupt, placing the SLIC in the correct state; configuring the data transmission time slot of each channel of the CODEC chip and the gain control of the CODEC chip; receiving and processing the AC48302 data packet processing interrupt, and the AC48302 passes the interrupt mode every time a voice data packet is processed. Inform the router CPU to read the data in the current Buffer or write the next packet to the Buffer.

This article uses the FXS interface, as long as the part of the circuit behind the CODEC slightly modified to achieve FXO or E&M interface functions. Currently, the voice card solution has been widely adopted in router products.