Design of Long Distance Transmission External Bus of Base Linear CCD

Linear array CCDs are extremely fast in applications in the field of image sensing and measurement technology. In order to meet the engineering needs of adaptive measurement, a linear CCD-based single coaxial cable bidirectional time division multiplexing transmission external bus was designed.

In a data acquisition measurement system, the maximum amplitude of the CCD video signal needs to be adjusted to the full scale of the ADC. There are three determinants of the maximum amplitude of the CCD signal: the photoelectric sensitivity of the CCD device, the light integration time, and the illuminance. After the CCD device is selected, this value depends only on the light integration time and illuminance.

The light intensity varies frequently at different working sites and at different working sites. If the light integration time of the CCD device is fixed, the change in illuminance will result in a change in the amplitude of the CCD video output signal. What is actually desired is that in the case of varying illumination levels, the maximum amplitude of the video output signal should be kept stable, which can be achieved by adaptive control of the optical integration time. In the process of binarized data processing and pixel subdivision processing of the CCD signal, the measurement information of the detected object in one frame of data is often at the position of the boundary feature and the amplitude of the pixel signal, so the change of the light integration time is not The effect of static is measured.

1 Introduction to CCD device driver

Now take TOSHIBA's TCDl501C as an example, the driving pulse waveform is shown in Figure 1.

When the SH signal is low, the potential well under the Φ1 (including Φ1O and Φ1E) electrodes is isolated from the memory gate well, and the CCD is in the light integration state; when SH is at the high level, the deep well formed under the SH electrode communicates The storage gate potential well and the potential well under the Φ1 electrode, the signal charge packets are all transferred to the shift register, and then sequentially shifted by the action of Φ1E, O, B and Φ1E, O, B pulses, and finally the output circuit is controlled by the OS end. Output.

The pulse period of SH is the light integration time. The amplitude of the pixel signal is controlled. By changing the pulse period of SH, the maximum amplitude of the video output is kept at the full scale of the ADC, thereby achieving adaptive control of the optical integration time.

2 system components

The acquisition system consists of three major parts: a CCD sensor head, a signal acquisition board, and a microcomputer. A single coaxial cable is used between the sensing head and the acquisition board as a bidirectional multiplexing transmission bus. The principle block diagram is shown in FIG. 2 .

The driving signals of the CCD are generated by the CPLD, and the video output is passed through the driver into the coaxial cable. The signal acquisition board adopts the ISA port and the microcomputer interface, and the FPGA uses the FPGA as the logic controller of the circuit. The optical integration pulse is generated by the FPGA, and the cycle adjustment is controlled by the FPGA VHDL software or the microcomputer acquisition software. Under the control of the interface protocol, the CCD video signal and the optical integrated pulse signal are bidirectional time-division multiplexed single coaxial cable as the signal and control transmission bus.

3 bus electrical interface principle

After the crystal oscillator is selected in the CCD sensor head, the signal frequencies of Φ1 and Φ2 are also determined. The CCD pixel video signal shift output time is also fixed. For example: TCDl501C has a total of 5,076 pixels (except 5000 exposure pixels, there are also the first 64 and the last 12 dummy), the crystal frequency is 20MHz, the Φ1 and Φ2 frequencies of the CPLD output are 2.5MHz, the video output rate It is 5MHz, so the output time of one frame of CCD signal is 5076/5MHz=1.0152ms. If the light integration time is 2ms, the CCD output is empty operation for the remaining lms, and the video signal amplitude is close to the clamp high level. The bus principle and control signal timing relationship diagram is shown in Figure 3.

The system sets the switching level at both ends of the coaxial cable in the initial state of power-on, so that the optical integration channel is turned on. It can be seen from the timing relationship that the falling edge of the light integration pulse starts the internal logic counter of the ISA board and the CCD sensor head, and at the same time, the switch control signals at both ends of the cable are switched from the optical integration channel to the CCD signal channel. Because the CCD device first outputs a certain number of dummy signals, the switching time of the selected SPDT (single pole double throw) switch is much smaller than the total output time of the previous dummy signal, so the time when the switch is switched to the CCD signal channel is The output of the exposure pixel signal has no effect. When counting to 5076 or 5064 (excluding the last 12 dummy), the two switch control signals at both ends of the cable change polarity again, causing the cable to switch to the optical integrated pulse signal path. In fact, as long as the channel switching is completed at any time before the next optical integration pulse arrives.

The most obvious and straightforward design is to use another standard bus (such as 422 bus) to specifically transmit the light integration control signal output by the ISA board, and the CCD video signal monopolizes the coaxial cable, which can also meet the engineering requirements. Requirements; and the transmission distance and anti-interference performance of the 422 bus twisted pair in harsh environments are also acceptable.

However, in comparison, the single coaxial cable bidirectional multiplexing bus is more advantageous.

First, the principle is more concise and practical, and its interface protocol is simpler than the 422 interface protocol;

Second, the intervention of the switch at both ends does not affect the transmission of the video signal, and the switching of the switch is outside the two ends of the CCD signal, and the transient voltage or voltage fluctuation that may be generated may not affect the effective signal of the entire frame;

Third, the generation of control signals is also very convenient. Anyone familiar with VHDL or Verilog language knows that in CPLD or FPGA programming, a new counter (or a counter is set up) and several count judgment control commands are added, and an external pin output control signal is locked to implement SPDT. Switch control function;

Figure 6

Fourth, the superiority of bus bandwidth and transmission distance is obvious. Compared with the bandwidth of 400MHz coaxial cable and the transmission distance of 300m~500m, the twisted pair is obviously inferior;

Fifth, the external connection line is saved and the installation is simple. E.g. An ISA acquisition board collects 4 CCD sensor heads. If a 422 bus interface is used to transmit optical integration pulses, 4 sets of 8 twisted pairs are required, and a single coaxial cable bidirectional time division multiplexing transmission bus is used. Coaxial cable is enough, and the connection operation is simple;

Figure 7

Sixth, the anti-interference of coaxial cable is better than that of twisted pair, which better meets the strict requirements of engineering practicality.

Figure 8

The single coaxial cable bidirectional multiplexing transmission external bus has been applied to a data acquisition system of a high precision CCD angle sensor.

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