315MHz/434MH based on MC33591/MC33592

Abstract: A 315MHz/434MHz OOK/FSK receiving circuit based on MC33591/MC33592 is designed. The data rate of this circuit is 1~11kbaud, the sensitivity of OOK/FSK is -105dBm, the fastest wake-up time is 1ms, and the power supply voltage is : VGND-0.3~5.5V, the power supply current is 7.4mA in the running and configuration mode, and the current consumption in standby mode is 250μA. In addition, the receiving circuit also has a three-wire SPI interface, which can directly interface with the microcontroller.

The MC33591/MC33592 is a monolithic integrated receiver with a 660kHz mid-band pass filter, a complete VCO, a mirror-removable mixer, a Manchester coded clock regeneration circuit, and a complete SPI interface. Can be used to design 315MHz / 434MHz OOK / FSK receiving circuit.

1 Pin Function of MC33591/ MC33592

The MC33591 is available in an LQFP24 package with pinouts as shown in Figure 1. The function of each pin is listed in Table 1.

Table 1 MC33591/MC33592 pin function description

2 internal structure and working principle

The RF section of the MC33591/MC33592 consists of a mixer that eliminates image interference, a 660kHz mid-band pass filter, an automatic gain control stage, and an OOK/FSK demodulator. The control section contains the data manager, configuration registers, serial interface, state controller, and so on. Its SPI interface allows programming of the modulation scheme. The circuit's data can be output from the comparator or output from the SPI port when the data manager is enabled.

2.1 Local Oscillator

Since the PLL loop filter has been integrated into the IC, the component values ​​in the actual application can be slightly improved by an external filter at the PFD pin according to the local oscillator parameters. The user can select the best working condition by attaching an external filter. The phase-locked loop circuit gain can be programmed by the PG bit. When this bit is 1, the loop is in a low gain state.

2.2 Communication Protocol

When communicating with the MC33591/MC33592, the duty ratio of the data after Manchester encoding is 48% to 52% in the OOK mode and 45% to 55% in the FSK mode. In addition, the communication protocol code also includes Preamble, ID, Header word, data, and the like. The content of the ID (recognition) word is encoded in Manchester and is preloaded into configuration register 2 in the circuit. The recognition word transmission rate is consistent with the numerical transmission rate.

In order to be different from the identification or header code, the content of the preamble must be carefully defined.

The header word should be the 4-bit Manchester code "0110" or its complement.

General data (Data) should follow the header without any delay. The data ends with an information end command, End-of-Message EOM?, which consists of two consecutive NRZs of 1 or 0. When FSK modulation is used, the data is terminated by an EOM and cannot simply be terminated by the RF signal.

Figure 2 shows a complete signal with a preamble, an identification word, a header word followed by 2 data bits and an end word. The preamble is usually placed before the words of the identification and header.

Figure 3 is a schematic diagram of a complete signal using ID detection. When the receiver enters standby mode, the setup time typically required is typically 1 ms.

2.3 Data Manager

The Data Manager function module has five purposes: ID (identification) word detection, header recognition, clock regeneration, data output and clock regeneration on the SPI channel, and information end detection.

2.4 serial interface

The receiver (ROMEO2) and the microcontroller typically communicate via a serial external interface SPI (Serial Peripheral Interface). If the SPI interface is not used, the reset terminal POR ? Power On Reset? will set the receiver to the default structure to complete the correct operation. The SPI interface operates through the following three inputs/outputs:

(1) serial clock SCLK;

(2) The main control output controlled input MOSI;

(3) The master input is controlled to output MISO.

The master clock synchronizes the data input/output through MOSI and MISO, and the master and slave can exchange one byte of information in 8 clock cycles. The SCLK clock is generated by the master device and input to the slave device during operation. The MOSI is configured as an input in the master device and as an output line in the slave device; when the MISI line of the master device is configured as an output, it acts as an input line in the slave device.

The MISO and MOSI lines generally transmit serial data in one direction, and the highest bit is transmitted first. Data is active on the falling edge of SCLK and moves on the rising edge of SCLK. When there is no data output, SCLK and MOSI are forced low. When using Motorola's microcontroller, its clock phase and polarity control bits, SPI, must be set to CPOL=0, CPHA=1.

2.5 Configuration Register

In configuration mode, as long as the reset terminal (RESETB) is held low for a long time, the microcontroller will provide the clock signal as the master on SCLK and provide the control and configuration bits on the MOSI line. If the default configuration is not used, the microcontroller (MCU) will change the configuration by writing a configuration word to the configuration register. The contents of the configuration registers can be returned to the microcontroller for detection.

When the RESETB pin is high, if the data manager is enabled (DME = 1), the receiver will transmit the received data as the master on the MOSI line and transmit the received clock signal on SCLK.

image 3

When the receiver SPI changes from master (operation mode) to slave (configuration mode) or from slave to master, the SPI recommendation in the MCU is set to slave before mode conversion.

When the power is turned on, the POR first resets the internal registers so that the receiver system is set to the default mode. In this configuration, the SPI is not enabled and the receiver will send raw data on the MOSI line. In fact, the default configuration allows the circuit to operate as a stand-alone receiver with no external control.

The MC33591/MC33592 has three configuration registers, CR1 to CR3. Configuration register 1 (CR1) controls the access (read or write) of three registers, mainly used to select the carrier frequency, set the data modulation mode, control the strobe oscillator enable, define the strobe ratio, and control the data manager. Ability to define headers, etc. Configuration Register 2 (CR2) is used to define the contents of the identification word. Configuration Register 3 (CR3) is used to define the data rate, set the mixer gain, control the conversion of the MIXOUT pin, set the phase comparator gain, and more.

2.6 Receiver mode

After power-on reset, the receiver generally has three different modes, the first one is the sleep mode, which is the low power mode. The second is the configuration mode, which is used to read and write internal registers. In this mode, the SPI is in the slave position and the receiver is enabled. The crystal oscillator oscillates to generate a clock signal for the SPI. The demodulated data can be read by the DMDAT, but cannot be sent via the SPI. The third is the working mode, in which the receiver can wait for a radio frequency signal or receive information.

3 MC33591/592 application circuit

The application circuit of MC33591/MC33592 is shown as in Fig. 4. The circuit should select a 9.864375MHz crystal at 315MHz and a 13.580625MHz crystal at 434MHz. When using FSK modulation, the relationship between the value of the low-pass filter capacitor C2 in FIG. 4 and the data rate is as listed in Table 2.

Table 2 Relationship between C2 and data rate when using FSK modulation

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