Optimize automotive infotainment and information communication systems with FPGA coprocessors

High-end automotive infotainment systems that integrate data communications, local services, and video entertainment require high-performance programmable processing technology support, and integrating FPGA coprocessors into mainstream automotive ICT architectures is the ideal solution. This paper presents the requirements for automotive entertainment systems, discusses the mainstream system architecture, and describes how to integrate FPGA coprocessors into hardware and software architectures to meet high-performance processing requirements, flexibility requirements, and cost reduction goals.

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Entertainment electronics is becoming a major aspect of the differentiation between luxury cars, driving the rapid development of its performance and functionality. How to compromise performance, cost and flexibility requirements is a challenge for design engineers. High-end applications include satellite radio, rear seat entertainment, navigation, various types of audio playback, speech synthesis and recognition, and other new applications.

The core technology used in automotive entertainment systems is fundamentally different from traditional automotive applications. Unlike other areas of automotive electronics, these entertainment applications are used every day, and demand is constantly changing. In addition, outdated entertainment systems will be a major obstacle to new car sales and will affect car resale prices and rental prices.

Technical requirements for in-car entertainment systems

Traditional automotive electronics are driven by a comprehensive standardization with long product life, a wider temperature range, and lower cost requirements, and in-vehicle entertainment systems basically meet these requirements. Design engineers need to design long-lived systems and adapt to the rapid development of system functions. These requirements require a high degree of flexibility and performance that is not available with traditional Application Specific Standard Product (ASSP) based system architectures.

The basic architecture of the in-vehicle entertainment system now designed to support flat panel displays, dynamic maps and car information can be displayed through a graphical human interface. These architectures are surrounded by highly standardized microcontrollers, various standard interfaces, and simple hardware accelerators that support low-end graphics processing. This architecture can meet the mid-level entertainment system requirements of the automotive market at very low cost, and can be extended to high-end applications to meet the requirements of the top luxury automotive market. Video image processing and communication are typical top-level applications. The various standards supporting these applications include MPEG2, MPEG4 and H.264 for video, as well as GSM/EDGE, WCDMA, 1XEVDO, satellite radio, satellite TV, digital video broadcasting and WiFi for communications, all of which rely on evolving Signal processing algorithms that require particularly high programmable processing performance.

There are currently three semiconductor technologies available to implement these highly complex algorithms: programmable digital signal processors (DSPs), ASSPs, and field programmable gate arrays (FPGAs). DSP is a high-performance programmable processor designed for signal processing. The DSP processor has high flexibility, low power consumption, and high cost performance. However, it has no hardware acceleration function and cannot provide advanced image processing and wireless communication algorithms. The computing power required; typically an ASSP with a DSP processor can provide an optimized solution for simple video or communication standards, but cannot be programmed to accommodate different standards; FPGAs are not only highly processing but also programmable. Therefore, it can meet a variety of applications and standards. Unlike the other two technologies, the flexibility and performance of the FPGA meets the requirements of all potential algorithms.

Figure 1

FPGA coprocessor application

The information communication infrastructure mentioned above requires additional processing chips to handle high-end applications, typically ASICs and ASSPs, which are integrated with the processor through a memory or video processing bus to become application-specific coprocessors. It is a very good idea to replace this specific application hardware with an FPGA. The application that integrates the FPGA and the processor is called FPGA coprocessing. This use of FPGAs can download new application-specific accelerators to the FPGA as required to assist in any high-performance application. This concept is widely used in advanced military multi-standard radios, commonly referred to as software-defined radio (SDR) technology. With SDR technology, a single radio can automatically adapt to different radio standards with simple push buttons, which not only helps the device adapt to future applications, but also reduces the number of custom processors that are idle when performing different tasks. This software radio technology can also be used for in-vehicle communication and video applications.

The flexibility of FPGAs in video processing and wireless connectivity also saves on equipment costs and increases the value of the system. The current basic architecture requires an ASSP to support each new video codec or wireless standard. Replacing multiple ASSPs with one FPGA can reduce the number of times that must be configured and maintained during the life of the vehicle. Extending the basic architecture of in-vehicle entertainment systems to include FPGAs provides a programmable single high-end platform that covers a wider range of video and wireless standards and performance. This method is also suitable for use in advanced automotive entertainment system architectures.

Delphi Delco Electronic Systems has released an example of an advanced automotive entertainment system architecture. The platform uses a standard SH-4 microprocessor and a Hitachi HD64404 "Amanda" ASIC device to provide the basic functionality required by the 80% mid-size automotive market. The system provides a general-purpose control processor with a standard API layer that abstracts hardware peripherals and coprocessors. The ASIC provides basic peripheral functions and an integrated graphics processor that supports interactive graphics and extended functions, but does not provide video codecs or other DSP functions. The system provides the basic functionality required for all entertainment devices, but still requires an additional ASIC or ASSP for video codec and wireless communication.

Figure II

The Amanda chip in the Delphi architecture (see Figures 1, 2) uses two processing buses, the Pixel bus for high-performance data streams such as video processing and the register bus for control, both of which are connected to the SH-4. MPX bus and external memory interface. This perfect combination of bus and memory interfaces is a good support for flexible video codecs and wireless communication platforms based on FPGA coprocessors.

FPGA co-processing allows the FPGA to be tightly integrated with the control or DSP processor, thus sharing most of the algorithm processing tasks while preserving the standard programming interface on the control processor. This integration works best when the algorithm's main data stream resides on the FPGA or associated memory. The algorithm is controlled by a slow control signal from the control processor.

This type of architecture can be applied to wireless communications, supporting digital processing in GSM/EDGE, WCDMA, 1xEVD0, and various 802.11 standards over a single FPGA. Other solutions can only be dedicated hardware design for each standard, but doing so would double the cost and board area.

In addition, multi-standard video codec including MPEG2, MPEG4 and H.264 can be completed by a single FPGA after applying FPGA co-processing in image processing. In fact, the same FPGA as in wireless communication applications can be used here.

The FPGA coprocessor is integrated with the processor-based system through a direct memory access (DMA) interface. The software layer running on the embedded processor provides an application interface for each coprocessor, and each coprocessor has an initialization routine that loads the FPGA with the correct application coprocessor. After the application is initialized, the software calls the coprocessor control parameters, timing, and data streams into and out of the coprocessor. Depending on the implementation standard, there may be a high level of interaction between the FPGA coprocessor and the control processor, or the FPGA coprocessor may work completely independently. In this case, the control processor simply loads the algorithm and then is in an independent state.

Each program image loaded into the FPGA needs to be integrated into the peripheral system. The programmable functionality of an FPGA requires a well-defined system interface to implement because each FPGA-based accelerator relies on it to communicate. Usually FPGAs have multiple interfaces to the controller, memory, and other peripherals or connectors. An FPGA may contain multiple coprocessors at the same time. These coprocessors share an interface to the control processor. Each peripheral device or coprocessor can have an additional bus for high performance data stream processing.

In a video codec, there is typically one input source and one output target. The video input interface in the Delphi system architecture is part of the Amanda ASIC and uses the ITU-R BT.656 interface for video streaming. This interface can later be extended and managed by an ASIC to suit different types of displays. The FPGA may need to be connected to the other two buses, the memory bus on the ASIC chip and the PCI/MPX bus of the main control processor. With these three connections, the FPGA can support high-bandwidth video and communications applications.

FPGAs can provide a reprogrammable platform for a specific application processing architecture to compensate for the deficiencies of the main processor. However, FPGA programs are fundamentally different from programs with standard processor architectures. FPGAs can provide high-performance hardware structures with programmable logic cells, routing resources, DSP processing blocks, memory, and I/O. The system architecture of the FPGA is implemented in the same way as the standard ASSP, that is, some special functions of the system are designed and implemented by hardware and software development tools. The output of these tools is a binary image file that, when loaded into the FPGA, will determine the functionality of all programmable logic cells, routing resources, DSP processing blocks, and more. The main processor can load these binary image files into the FPGA while the system is running. A variety of different program images can be created to support MPEG2, MPEG4, H.264, GSM/EDGE, WCDMA, 1xEVDO, GPS, 3D graphics accelerators or other algorithms that may be used in automotive information communication systems. Depending on the user's menu selection in the entertainment system, a particular application can be downloaded to the FPGA by the host processor and then controlled by the host processor.

FPGA for programmable functions requires a well-defined system interface

The main processor's control of a particular hardware accelerator is typically done through registers and memory interfaces, each controlling some aspects of the hardware accelerator's operation. This is the default synergy chip in the Delphi system, as will be the case for each coprocessor architecture loaded into the FPGA. With FPGAs, it is easy to handle tasks like normalized registers and memory interfaces to control the coprocessors programmed into the device. This standard interface defines how to read and write data to the coprocessor, how to start and stop reading and writing, how to reset, and a set of registers that control the operation of a particular application. All of these registers are part of the FPGA's internal linear address map, so software physical device drivers can easily access these registers.

The software physical device driver for the coprocessor has a higher level of abstraction than the hardware implemented register interface. The software driver provides a mapping from the system's algorithm parameters to the control registers, so the application software is very easy to write and maintain. Higher layer model device drivers remain fairly portable during the underlying hardware implementation changes. The software architecture in the Delphi system can support software or hardware coprocessors to implement algorithms. It provides several layers of abstraction that separate the algorithm implementation from the physical implementation in software or hardware. The FPGA coprocessor is ideal for Delphi's software and hardware architecture.

FPGAs are designed for use in many systems with a basic architecture similar to the Delphi system architecture. These systems contain more than one control or DSP processor and use FPGAs to accelerate tasks that require high performance processing. The key challenges in implementing FPGA coprocessors are the following: designing different hardware accelerators for FPGAs; integrating hardware accelerators with external control processors; and creating software layers that control hardware accelerators. All required hardware accelerators include mainstream algorithms for video and communication applications. Such applications will have a broad market in the future, and this market will develop more special standard intellectual property (IP) hardware accelerator professional design companies that can provide ready-made products that can be directly used in advanced low-cost FPGAs. algorithm. In addition, commercial IP modules designed for MPEG2, MPEG4, H.264, WiFi, and other video and communication standards can be purchased. Figure 3 is a block diagram of the IP module of the MPEG4 decoder introduced by Amphion, which can be used in ASIC or FPGA.

image 3

SOPC Builder application

The next step is to integrate the hardware accelerators in the FPGA with the external bus for control, data input and output. Design engineers can easily implement this step with new development tools. Design engineers can use the system integration tool SOPC Builder from Altera to select the appropriate IP module from the list of available IPs. At the time of selection, the tool provides a parameterized menu that allows the user to control different architectural options before implementation. Once the parameters are set, the module is included in the list of other peripherals and processors that the engineer is ready to integrate. Once each IP module is selected and parameters are set, it needs to be integrated into the processing architecture.

SOPC Builder enables design engineers to define high-performance switch architectures and connect various hardware accelerators and peripheral devices to external host processors through a switch fabric. The definition of this switch architecture can be done with a click of the mouse on the intuitive matrix of the module interconnect. Once defined, SOPC Builder automatically assembles the individual IPs and then generates a description of the hardware description language and automatically integrates them into the final FPGA program. The final program is downloaded to the FPGA during runtime to implement a coprocessor for a particular algorithm.

After hardware integration is complete, software physical devices are required to separate high-level software control from the specific register and memory-mapped architecture used to control the hardware accelerator. The registers and memory used to control the hardware accelerator are standard components of the parameterized IP module. However, the integration of multiple peripheral devices with an accelerator requires a register and memory map that implements all programmable features on the FPGA. SOPC Builder automatically creates such registers and memory maps when assembling IP into a user-defined switch fabric.

Each IP module contains a set of pre-defined software physical device drivers that are primarily used by external host processors to control the IP blocks. SOPC Builder automatically assembles individual software physical device drivers and automatically associates each drive with a register and memory map associated with the IP module it controls. So SOPC Builder can automatically create and integrate the hardware and software architecture of the FPGA coprocessor and control processor in this way. SOPC Builder meets the rapidly evolving performance requirements of FPGAs and adapts to the ability of FPGAs to continuously enhance their application in complex system implementations.

Factors driving the rapid development of FPGA technology

Programmable logic devices have grown rapidly since their introduction 20 years ago, and have evolved from low-level glue logic to the lowest cost, highest programmable processing performance available today. The two key elements driving FPGA performance and cost are the evolution of FPGA architecture and the way FPGAs use semiconductor technology. The programmable logic cell array provided by the FPGA architecture is combined with programmable routing resources. In early low-density FPGAs, this architecture enabled the interconnection of simple processing units. As FPGA densities increase, array architectures can provide highly parallel processing capabilities. The entire processing array of the FPGA architecture now includes memory modules, DSP blocks, and programmable I/O, making it easy to meet the performance requirements of automotive information processing systems.

Another important driver for FPGA development is process technology and its impact on performance and cost. Using the latest generation of process technology can increase the density and performance of FPGAs and reduce the cost of FPGAs. At the same time, the widespread use of FPGAs in turn promotes the development of process technology. FPGAs are extremely valuable for the development of semiconductor process technology because they use a regular structure that can be put into mass production early in their life cycle. The regular structure of the FPGA is very convenient for collecting statistical data in product defect testing, which is very important for accurately adjusting the process technology to achieve higher manufacturing yield. The symbiotic relationship between FPGA and process technology continues to increase the density of FPGAs and reduce the cost of devices. Therefore, compared to dedicated ASICs and ASSPs, Altera's Cyclone series of low-cost FPGAs are currently highly competitive in terms of price.

Summary of this article

The technology and differentiation of automotive entertainment systems are constantly evolving. The advanced system architecture serves most of the mainstream automotive market and differentiates high-end products with additional ASSP and software support. FPGAs provide a high-performance and flexible co-processing platform that combines the functionality of many ASSPs into a single reprogrammable platform. The FPGA coprocessor is ideal for mainstream automotive entertainment architectures such as the Delphi architecture. By using the FPGA coprocessor as part of the high-end automotive entertainment system architecture, automotive companies can provide a variety of high-end video and communication capabilities that ASSPs cannot provide separately through software programming. The flexible, high-end automotive entertainment architecture leverages FPGAs to deliver new capabilities throughout the life of a car or even the entire car. The ability to enhance the functionality of the car entertainment system during the sales and after-sales phase can increase the value of car sales and after-sales, while the resale value of previously rented cars remains the main source of profit for car manufacturers.

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