Which affects gate leakage and dynamic power density

The large number of new nodes, half nodes, and the generation of each number between them is confusing with chip manufacturers. Although most people think that having a choice is a good thing, it is not clear which one or which choices are the best.

The question is which IP is available for these nodes; how different is the IP from other nodes in terms of power, performance, area, and sensitivity to various noise types; different versions of IP correspond to those different manufacturing faces for different nodes and nodelets The process is tested. Because most of the new node definitions are not yet clear. So, for which type of transistor will be used, which will affect gate leakage and dynamic power density, and how this will affect how much additional mask patterns are needed for adjacent IP and other components, now let's conclude It is still too early.

Ranjit Adhikary, vice president of marketing at ClioSoft, said: "Now, the number and name of nodes between different vendors are different. What is the performance of each PPA (performance, power, area)? Because PPA is the product that determines your design. The most basic factor of which IP to use. However, because there are too many choices, now you need to see which foundries provide it and which node it supports. For each IP, there may be different memory or cache, and because of the foundry, Categories and process nodes vary."

However, all major process nodes come in many types, with multiple partial nodes ranging from 22 nm to 3 nm. This raises questions about which IPs are available, whether it has adequate characterization and testing for each node, and whether it will support the time required for different end markets. This is not a problem for mobile devices. In the past few decades, mobile devices have dominated the chip market with relatively short product cycles, but for industrial and automotive applications it is quite another matter. The devices here require decades of support.

Navraj Nandra, senior marketing director at Synopsys' DesignWare Analog and MSIP Solutions Group, said: "We have never seen such a proliferation of foundry nodes. We have node names from 18nm to 1nm. But this requires management to commit to investing in a node. They want to see if hard IP is available, so you need an available SoC because you really want to see the chip test report for the IP used in the new node. This also requires an IP vendor investment. So the foundry may Something a little better will be found in terms of timing and ROI (such as high-speed memory interfaces or HBM-based products). But you may also spend a lot of money here, but you can't make money."

This seems to be the consensus of IP developers. Instead of supporting each node as they have in the past, they try to assess which nodes may generate enough yield to create a reasonable return on investment. Efforts don't always translate into profits, especially on advanced nodes, and wrong choices can be costly.

Marc Greenberg, Head of Product Marketing, DDR, HBM, Flash/Storage and MIPI at Cadence, said: "We all know that newer process mask patterns are more of a process capability (transistor density and power/speed). A compromise) guide, not any actual physical size of the process. The industry standard to date has been to point out key differences in the process – for example, SiON vs high-k/metal gate, whether EUV is used – Use the letter or symbol suffix to mark the process. But this may eventually become the new nodelet instead of the new suffix. At the 28nm node, we see many variants of the 28nm process, which are often incompatible with each other. A lot of work has been done to cover the changes in all of these process nodes. We have also seen some difficulties with the early finFET node takeoff, which is a bigger job for the IP industry, and this does not necessarily translate into sales. ."

What is a nodelet?

Marketing terminology is the main cause of confusion in nodelets. The numbers are also blurred until no one knows exactly what the numbers really mean. For example, TSMC and Samsung's so-called 5nm are actually 7nm for Intel, GlobalFoundries and Imec, as well as for 10/7nm and 5/3nm. Most importantly, these nodes are available in different versions based on low power, high performance, and cost based, each with its own characteristics.

Synopsys' Nandra said: "The expected process for a given node is that if it is in production, you can optimize the node. For example, you have 28nm, you know it works well, and the defect density is a fixed percentage. To improve this, you can compress it a bit and give it a new name, such as 22nm. But that doesn't mean it has a 22nm gate length. You just did something to make it have a better density. For the IP industry, this shouldn't be a big change. However, when it comes to high-speed versions, due to the extraction, simulation, resistance, capacitance and sensing relationships of the package, the effect of optical shrinking on the transistor, all of which will result. A lot of rework. You need to completely revalidate the IP. Post-layout parasitic extraction can be a considerable challenge. Or you need to complete a new test chip to make sure you don't miss anything."

Prior to the finFET era, the foundry will adopt Intel's node and half-node "Tick-Tock" strategy. However, after 28 nm, the node numbers begin to split into numbered segments that may or may not occur, in large part because there are not enough IP choices to make them workable. Although large IP providers will follow suit, at least for now, it is unclear whether other vendors in the industry can keep up.

Cadence's Greenberg said: "The 12/11nm node has also received good support from the foundry. The guidance we got from the foundry is that it should be a 'simple' IP port from 16/14nm to 12/11nm. However, In some cases, we have taken steps to produce and describe new IP test chips for these nodes. Some foundries are supporting 10nm half nodes and its 8nm nodelets, we are supporting the chosen IP. At 7nm, we have A powerful node, Cadence widely supports the latest advanced technology IP. It is not yet certain whether there will be a widely supported 6nm node, or whether the industry will jump to 5nm."

Nandra pointed out that this work may be more expensive than IP developers expect. “If you can, customers will ask for chip-based feature reporting. If you have a strong analog/mixed-signal part, customers will be more conservative. They want to see more chips.”

More and more details of the devil

For nodes of 28 nm and below, the miniaturization of the nodes seems to have no end. The current estimate is between 1.2 and 1.3 nm, although the exact number may vary depending on the type of gate FET vs finFET, for example, introducing lithography options such as directional self-assembly and high-NA EUV to extend device miniaturization Proportions, as well as advances in metering, etching, and deposition.

Roland Jancke, head of design methodology at Fraunhofer's Engineering Adaptive Systems Division, said: "7nm technology is under development, 5nm and 4nm have been announced. In order to improve the performance of this technology, the integrated device is extremely optimized. Therefore, it appears in the technology node. A large number of independent device types, such as I/O devices, core devices, pull-up and pull-down devices, and several threshold voltage versions of the device. This trend has greatly increased the technical characteristics, qualifications, and workload of model development. Need to be repeated after each process change."

In addition, these devices are becoming increasingly sensitive to physical factors such as temperature and noise. The threshold voltages respond differently at different temperatures, and the sensitivity increases as each node shrinks. The result is a more detailed description than in the past.

Craig Hampel, Rambus's chief scientist, said: "We made adjustments in the high Vt segment and didn't solve the problem at first. So now if we have high Vt, we will improve the level of characterization. In the past few years As the nodes migrated to 16nm, our characterization has almost quadrupled."

After that, the problem of each new node will become more and more serious. However, the added characterization is no longer just a problem with lower nodes. There are also many variations of the old node process, and there are more use cases involving security and reliability, even more on the older nodes.

Fraunhofer's Jancke said: "For mixed-signal technology nodes down to 110nm, there is a huge diversity in a given node. For ultra-low power, high power, high voltage, RF and optical applications, MEMS devices, etc. Etc. There is usually a separate version of the technology. On the other hand, designers tend to integrate several parts of the SoC into a silicon die, which has led to the interest and development of combination technologies such as BCD processes for power integrated circuits."

This also makes it more difficult to evaluate which IP is most effective because an IP needs to work with other IPs. All of this affects time to market, overall cost, and power/performance. Even worse, if there are fewer options available, it may limit the functionality of the device.

Adhikary of ClioSoft said: "There are a lot of questions that need to be answered by IP. If you want higher performance, get IP from the 9nm node and move it to 5nm, how much area can you get? How to get a new node? It can take three to four months to develop an IP. But can you really benefit from area and performance? If you want to do multiple times a year, what version of IP do you use? If others Do you use the same PDK library with this IP? If you are integrating IP with other IPs, you really need to make sure you have the same version of PDK. We are now more concerned with the PDK version and what version of the library is in use. You need More and more details are being understood."

From the perspective of IP developers, this is also problematic. Synopsys' Nandra said: "The difference in this kind of work will obviously appear on the updated technology version. It takes longer to develop 7nm or 10nm IP than 14nm or 28nm, and this work is usually two to four of the original workload. Double."

in conclusion

All of this is complicated by new node, nodelet, and node naming conventions. The foundry has stepped up its efforts to provide more data, and IP vendors have more characterizations than in the past because the tolerances of each new node and nodelet have become even tighter.

Greenberg said: "Everyone started learning from the 28nm era. Although there will always be process advancements in the life cycle of the node, the foundry has better provided early guidance to IP providers and guided the basic process. The difference between its variants. In some cases, this allows us to develop mixed-signal IPs for nodes developed from the same IP and their nodelets or multiple suffixes. Contemporary factories can communicate these plans to us in advance. When it helps us provide a wider range of IP, and ultimately helps reduce costs."

But at least for the foreseeable future, managing node names, numbers, and IP versions will become more difficult. There are too many choices and potential interactions, and there are too many variations that are unclear or undefined.

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