Design of Four-Channel MPEG-4 Video Surveillance System Based on MPC850

This article refers to the address: http://

Abstract : This paper introduces the embedded communication controller chip MPC850 and MPEG-4 digital video compression chip IME6400 based on PowerPC core, and designs and implements a new MPEG-4 digital video monitoring system.
Keywords : embedded system; MPC850; IME6400; hardware development platform

This
paper uses MPEG-4 encoding chip IME6400 to realize embedded MPEG-4 audio and video encoding, and is applied to the actual monitoring system. The solution overcomes the shortcomings of traditional video surveillance systems and can be used for local storage as well as for remote monitoring via fiber optic networks and Ethernet. The overall design of the system is shown in Figure 1.

MPEG-4 video compression module design
The MPEG-4 video compression module design is shown in Figure 2. The design block diagram is described in detail below:
1. Four BT829Bs complete PAL video A/D sampling, and four PCM1801 complete audio A/D sampling.
2. The IME6400 receives the video data of the CCIR-601 interface from the BT829B, receives the A/D sample data of the I2S from the PCM1801, and performs independent MPEG-4 compression encoding for each audio and video signal.
3. The chip select signal of the CPU controls which data channel is turned on.
4. The IOST6400's HOST interface address and data bus are connected to the MPC850 after being driven;
5. The audio I2S clock is generated by the crystal circuit.
6. The four-input AND gate 7421 ensures that the data channel is opened when one of the four slices is selected.

IME6400 design
The IME6400's VIDEO interface supports the CCIR-601 16bit interface with a maximum horizontal and vertical orientation of up to 2048 pixels. The video A/D sampling in this system is completed by BT829B, and the VIDEO interface clock is provided by CLKX1 of BT829B. Audio A/D sampling is done by PCM1801. This is a 5V powered supply that supports multi-rate 16-bit A/D encoded audio sampling chips. The data sampling rate of analog audio and video signals can be programmed.

The external HOST interface of the IME6400 is used to transmit the encoded data stream. There are four modes. They are determined by a MODE pin. The mode selected for this design is: Synchronous Burst Type1, MODE[1:0] pin = 2'b 01.

The clock of the HOST interface can be provided by MCLK or FRD. Determined by the value of USEOCK. In this design, USEOCK=1, FRD is used as the internal clock source. This 27MHz clock source is provided by the main control board.

If you use an internal boot ROM, the IME6400 does not require an external ROM, but in external boot mode, it requires a ROM interface. The external ROM can be up to 4M. This design EXTBOOT uses jumper control to boot with external or internal ROM. The external ROM of this design is 28C256, which is powered by 256K and 5V. The 27MHz clock of MCLK is provided by the main control board.

The I2C interface of the IME6400 supports only the main mode and does not support the slave mode. If 27MHz is used as the master clock, the IME6400 supports interface rates from 41Hz to 1.6875MHz.

In order to compress video and audio data and store the encoded stream, an external SDRAM is required. The size is related to the size and mode of the image to be compressed. The SDRAM selected for this design is 2MX32. The external SDRAM that the IME6400 can access can be up to 2Gbits. The current design size is 11 rows and 8 columns of addresses.

The clock of the SDRAM is three or four times the MCLK clock, which is determined by the value of the DIV34. In this design, the MCLK clock is 27MHz, and the MCLK clock is selected three times, so the SDRAM clock is 81MHz.

MPC850 communication interface design MPC850 (hereinafter referred to as 850) communication controller chip based on PowerPC core, based on RISC architecture, integrated 32-bit microprocessor and a variety of peripheral interfaces, with powerful communication and network protocol processing capabilities .

The system utilizes 850 powerful communication capabilities, with appropriate interface chips, realizes two optical ports and two Ethernet ports, and realizes the ability to plug up to four hard disks with FPGA, as shown in Figure 3. In the design of this module, there are mainly the following key points.

850 generates IP178A reset The reset signal of IP178A is controlled by 850 with pin 850-PD[8]. Reset is required during initialization. The reset time must be greater than 1ms. If you need to change the configuration of IP178A, you need to reset it after the configuration is completed. The same reset time must be greater than 1ms.

850 change the control of IP178A configuration Change the configuration of IP178A by programming 93C46 and then reset IP178A. There are two CD4053s on the front of the 93C46, which are used to select whether to read or write IP178A or 850 to 93C46. The selection signal is controlled by 850-850[3] (pull-down) of 850. Usually 850-PD[3] outputs high impedance or low level, at this time 93C46 is controlled by IP178A. Before changing the configuration of IP178A, output high level on 850-PD[3]. At this time, 93C46 is controlled by 850. After reading and writing operation, 850 controls 850-PD[3] output high impedance or low level, 93C46 Returned to IP178A control. After resetting IP178A, the new configuration takes effect.

850 Pair 93C46 Reconfiguration Read and write is implemented by programmable pin 850-PD[4:7]. 850-PD[4:7] correspond to PD[4]<->EESK, PD[5]<->EEDI, PD[6]<->EECS, and PD[7]<->EEDO, respectively.
850 operation of the IME6400

In the burst mode when reading compressed data, 4 NFULL[3:0] signals are directly input to 4 IRQ[3:0] of 850; 4 READY[3:0] signals of 4 IME 6400 are advanced FPGA, The READY signal generated by the FPGA to the TA of the 850 allows for convenient timing control. The IME6400 has two ways to download FIRMWARE. It can be selected by the jumper on pin P236 (EXTBOOT). The high level H is selected from the external 28C256 and the low level L is selected from the 850.

850 and IP178A connection 850 Ethernet port via LXT905 to Ethernet switch chip IP178A PORT2, two electrical ports (port3, port4) and two optical ports (port6, port7). The 850 changes the configuration of the IP178A by programming the 93C46 and resetting the IP178A.

System Testing and Advantages The system prototype has participated in the bidding of several security products, and the system has more outstanding advantages compared with similar products.

The application of hardware chips for MPEG-4 compression and embedded systems greatly improves the performance of the monitoring system, as shown in:
1. The recording and preview are equally clear, the image format can achieve D1, and the full dynamic bit rate can be controlled at 200Mb/hour.
2. Faster compression, no lag delay when playing live streams. Because it is hardware compression, the speed is faster than software compression and DSP-based systems, and more in line with current monitoring market requirements.
3. The reading of compressed data improves the reading speed by adopting the burst mode, which provides conditions for the adoption of the embedded CPU. And make the network transmission more smooth and stable.

Conclusion
This paper introduces and analyzes the MPC850 and IME6400 chips, and designs and implements an embedded MPEG-4 video surveillance system for commercial use. This solution is applicable to video monitoring of various information networks such as optical fiber and Ethernet.

references
1 Y. Pourmohammadi, K. Asrar Haghighi, A. Kaheel, HM Alnuweiri, ST Vuong; On the Design of a QoS-aware MPEG-4 Multimedia Server, IST2001.
2 R. Talluri, "Error-Resilient Video Coding in the ISO MPEG-4 Standard", IEEE communications Magazine, Vol. 36 No. 6, June 1998, pp. 112-119.

Others Fuses

Cutout Fuse Co., Ltd. , http://www.nsindoorfuse.com